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qwaserdf-@._
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Registered: ‎06-14-2018

Jtag to axi Master - dbg hub

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Good morning. Trying to carry out the lab 7 on in this tutorial ug936 "Vivado Design Suite Tutorial progamming and debugging".

 

I am crashing with this problem that I don't know how to solve.

 

When I open the new project with the IP (Jtag to axi Master)  example design, after generating the bitstream I receive this warning and I can't get the ILA opened:

WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'u_ila_0' at location '1:1-0' from probes file, since it cannot be found on the programmed device

 I try through adding this line to the .xdc, changing the clock connected to the dbg_hub, and maybe getting it being commanded by a free running clock

connect_debug_port dbg_hub/clk [get_nets clk_mmc]

This is exactly the clock I am picking.

Captura.PNG

 

 

The problem is I am getting still the same error, and I don't know how to pick a "freer" clock.

 

I also check as the programm suggested BSCAN_SWITCH_USER_MASK reflects the same as the user scan chain setting.

 

The fpga I am using is XC7Z020-1CLG400C, in the ZYBO Z7 developtmen kit.

 

Thank you for your time. Best regards.

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anunesgu
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2,362 Views
Registered: ‎02-09-2017

Hi qwaserdf-@._,

 

Your clock selection is probably correct, but since you are using a Zynq device, most likely that clock is being generated by the PS and forwarded to the PL for clocking the logic.

 

The issue is that you have to first initialize the PS using the script ps_init.tcl in the SDK (or just running a simple hello world program in the PS). That will initialize all the PS resources, including the clock generation.

 

Then you can go back to Vivado and program the PL using the bitstream.

 

The document Embedded Processor Hardware Design - UG940, Lab 1, has a guide through the whole process.

 

Thanks.

 

 

Andre Guerrero

Product Applications Engineer

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arpansur
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2,237 Views
Registered: ‎07-01-2015

Hi qwaserdf-@._,

 

What is the package pin used for clock in the XDC?

Are you using the package pin constraints for sysclk from the master XDC?

Thanks,
Arpan
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qwaserdf-@._
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Registered: ‎06-14-2018

Good morning Arpansur

 

The package pin is the U18.

 

set_property PACKAGE_PIN U18 [get_ports clk_p]

This is the line typed in th e XDC.

 

The problem I am having this time. I am trying to follow the steps descrived in the tutorial ug908 to "specify the user scan chain value as an option to hw_server start-up". Typing this command: "hw_server -e "set bscan-switch-user-mask 0010”", for changing from 1 to 2, as the AR# 64764 suggested.

I am getting this error: "Cannot create listening port: Socket bind error"

 

Thank you for your answer.

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anunesgu
Moderator
Moderator
2,363 Views
Registered: ‎02-09-2017

Hi qwaserdf-@._,

 

Your clock selection is probably correct, but since you are using a Zynq device, most likely that clock is being generated by the PS and forwarded to the PL for clocking the logic.

 

The issue is that you have to first initialize the PS using the script ps_init.tcl in the SDK (or just running a simple hello world program in the PS). That will initialize all the PS resources, including the clock generation.

 

Then you can go back to Vivado and program the PL using the bitstream.

 

The document Embedded Processor Hardware Design - UG940, Lab 1, has a guide through the whole process.

 

Thanks.

 

 

Andre Guerrero

Product Applications Engineer

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

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qwaserdf-@._
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Registered: ‎06-14-2018

Yes, that made it. Thanks a lot. Best regards.