04-14-2017 04:03 PM
I'm using ISE14.7 to target an xc3sd3400a-4cs484 and would like to insert a chipscope core (1 trigger port, approx 50 lines, 1024 samples, using only a few hundred LUTs) after synthesis. The project Maps without the core but fails mapping with the core. For some reason, inserting the core causes the number of slices used to double and DSP48A count to go from a dozen to 210. I have tried deleting/remaking the core, changing the port size, changing the number of match units and cleaning the project. Sounds like the either synthesis or map went off the rails. Can someone help me get it back on track?
Device utilization summary:
Selected Device : 3sd3400acs484-4
Number of Slices: 24946 out of 23872 104% (*)
Number of Slice Flip Flops: 19902 out of 47744 41%
Number of 4 input LUTs: 25490 out of 47744 53%
Number used as logic: 25433
Number used as Shift registers: 57
Number of IOs: 283
Number of bonded IOBs: 192 out of 309 62%
IOB Flip Flops: 2
Number of BRAMs: 15 out of 126 11%
Number of GCLKs: 3 out of 24 12%
Number of DCMs: 2 out of 8 25%
Number of DSP48s: 9 out of 126 7%
WARNING:Xst:1336 - (*) More than 100% of Device resources are used
Total Number Slice Registers: 23,531 out of 47,744 49%
Number used as Flip Flops: 22,387
Number used as Latches: 1,144
Number of 4 input LUTs: 28,077 out of 47,744 58%
Number of Slices containing only related logic: 32,879 out of 32,879 100%
Number of Slices containing unrelated logic: 0 out of 32,879 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 30,792 out of 47,744 64%
Number used as logic: 27,349
Number used as a route-thru: 2,715
Number used as Shift registers: 728
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
Number of bonded IOBs: 256 out of 309 82%
IOB Flip Flops: 39
IOB Latches: 3
Number of ODDR2s used: 2
Number of DDR_ALIGNMENT = NONE 2
Number of DDR_ALIGNMENT = C0 0
Number of DDR_ALIGNMENT = C1 0
Number of BUFGMUXs: 4 out of 24 16%
Number of DCMs: 2 out of 8 25%
Number of BSCANs: 1 out of 1 100%
Number of DSP48As: 210 out of 126 166% (OVERMAPPED)
Number of RAMB16BWERs: 18 out of 126 14%
Number of BSCAN_SPARTAN3As: 1 out of 1 100%
Number of RPM macros: 14
04-18-2017 03:27 AM - edited 04-18-2017 03:30 AM
Are you using core inserter flow?
It should not affect DSP. Can you please check the core utilization in case you are using core inserter flow?
Please go through page-40 of https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/chipscope_pro_sw_cores_ug029.pdf for core utilization.
04-19-2017 09:05 AM
Yes, I'm using the Core Inserter flow.
I have additional information from my recent work. The synthesis report only mentions about 9 DSP cores used but apparently does not count those from SysGen blocks. After using a much smaller chipscope core(56 lines down from about 100 lines) and removing some SysGen blocks, I was able to map my design and the map report showed 77 out of 120 DSP cores (used by sysgen blocks.)
Still, when I go instantiate a larger core, DSP usage sometimes spikes to >200 cores and Map fails. As the Map report shows, there are plenty of LUTs and BRAMs left. I understand the BRAMs and DSP cores are closely coupled on the 3aDSP chips. Could that have something to do with it?
At the moment it's working. Hope it stays that way.