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Explorer
Explorer
1,572 Views
Registered: ‎12-08-2007

Message: No debug cores, when trying to use ILA

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I am learning to use the ILA.

I create a half-adder, create an .xdc file (for Basys3 board).

After adding ILA IP from the catalog, I insert in VHDL the ILA component. Here is the VHDL code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main is
    Port ( clk100mhz: in std_logic; -- for the ILA
    
           x : in STD_LOGIC;
           y : in STD_LOGIC;
           s : buffer  STD_LOGIC; -- we need buffer in order to read it for ILA
           c : buffer  STD_LOGIC);
end main;

architecture Behavioral of main is

component ila_0
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
    probe1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END component;

begin

MYILA: ila_0 PORT map (clk => clk100mhz, probe0(1) => x, probe0(0) => y, probe1(1) => s, probe1(0) =>c);


s <= x xor y;
c <= x and y;

end Behavioral;

I run synthesis. I see two critical warnings in the synthesized design, which pertain to the clock100Mhz lines in the .xdc. (see enclosed, ). I am not sure what the warnings are because  all other lines in .xdc that regard the other nets do not give a warning.

Then, I choose "Set Up Debug" and I have 4 nets to debug. (see enclosed).

I run Implementation fine. I add in the bitstream settings a file .TCL which contains the following code:

set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

because I have most of the pins of the FPGA  are not used.

I then generate bitstream. I program the .bit to the FPGA.

I open the Hardware manager but I see a message that there are no debug cores. (see enclosed). 

So I cannot start the Logic Analyzer.

The design itself is programmed into the FPGA and I can validate the Half-Adder  manually (using Switches and Leds).

But I would like to run the Logic Analyzer.

 

Any advise?

 

Screen Shot 2018-12-31 at 13.15.06.png
Screen Shot 2018-12-31 at 11.54.50.png
Screen Shot 2018-12-31 at 13.21.15.png
Capture8.PNG
Screen Shot 2018-12-31 at 13.31.09.png
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1 Solution

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Moderator
Moderator
1,113 Views
Registered: ‎02-09-2017

Re: Message: No debug cores, when trying to use ILA

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Hi @dag1,

The problem is still that your ILA/dbg_hub cannot find the clock input.

I think I know why that's happening. First, you should note demote the DRC errors to warnings, you really have to fix those issues.

The DRC I am seeing is saying that the port clk100mhz is both unsconstrained (no pin placement) and does not have an electrical standard assigned to it.

Looking at your XDC file, I can see that those two constraints are there, but guess what? They are declared with capital letters (CLK100MHZ), while in your top file you have declared it with lower case letters (clk100mhz).

I'm pretty sure that Vivado is not finding those ports because the naming is case sensitive.

Please make a test, open your Sytmehsized design and run the following two commands:

get_ports {CLK100MHZ}
get_ports {clk100mhz}

See which ones returns a Null and which one returns an Object (I'm pretty sure the clk100mhz will be the one not Null).

change your XDC constraint to reflect the correct naming and run the Implementation again. That should make the DRC error go away and also get the ILA to receive it's clock.

Thanks,

Andre Guerrero

Product Applications Engineer

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Moderator
Moderator
1,540 Views
Registered: ‎02-09-2017

Re: Message: No debug cores, when trying to use ILA

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Hi @dag1,

To make things easier a bit, instead of instantiating the ILA in VHDL as you did, lets try to use the Set Up Debug Flow instead.

Just for a better understanding of the process, there are two ways of inserting the ILA into a Design: \

  • Inserting it right into the VHDL/Verilog code (just as you did);
  • Just do your main logic in VHDL/Verilog and do not insert any ILA until the Synthesis Process is done, at which point you will click on the Setup Debug button and do it through the GUI.

The Setup Debug method is the easier and faster way to do it. I'd recommend using the VHDL/Verilog Instantiation method just in more advanced cases, where the Setup Debug is not capable of doing it. You should avoid using both methods in the same design.

So to do so, you can remove the ILA IP you created from the catalog and remove any evidence of the ILA from your VHDL code. Carry on with the synthesis process and once you're done, please follow the Setup Debug Flow, as in the document Vivado Programming and Debugging - UG908, pg. 118 to 121.

Please reply back once you've done this process and let us know if you're still seeing issues, if there's any new errors/warnings, etc.

In addition, the "set_property" warning you are seeing is most likely because the object name doesn't exist yet (maybe it's a derived clock, which Vivado only knows it exists after the synthesis is done). Since you said that the logic itself is working, I would not worry about it for now, but we can look at it later too.

Thanks,

Andre Guerrero

Product Applications Engineer

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Moderator
Moderator
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Registered: ‎02-09-2017

Re: Message: No debug cores, when trying to use ILA

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Just to let you know, I noticed that there were two posts of yours with the same question, so I deleted one just so we concentrate our efforts on this one.

Thanks!

Andre Guerrero

Product Applications Engineer

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Explorer
Explorer
1,481 Views
Registered: ‎12-08-2007

Re: Message: No debug cores, when trying to use ILA

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Hi

 

I follow our suggestion and I start a new project.

HDL only has the Half Adder code. 

The new project has no ILA IP as you requested.

I run synthesis.

I do 

set up debug:

I open the NetList and I drag the following 4 signals into the "Nets to Debug" window:

c_OBUF

s_OBUF

x_IBUF

y_IBUF

I then see "Clock Domain" undefined for all four.

I Right Click,  Select Clock Domain, but get message that no clock domain found. I try to choose ALL_CLOCK, but get message "Nothing found for: ALL_CLOCK".

I assume that there needs to be some clock for sampling (although I have not yet at this point added ILA from the catalog) so I have added an input signal in the entity (in VHDL) which is CLK100MHZ.

The .xlc constraint file has all four signals, and the signal called CLK100MHZ (with the pin W5 on the Basys3 board). 

I can see it in the Schematic (unconnected) after synthesis. But still, I am unable to choose this clock for the purpose of Clock Domain.

So I am stuck here. (I followed p. 118 - 119 up to this point). So no ILA IP has been inserted .

 

What should I do to resolve this?

 

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Moderator
Moderator
1,457 Views
Registered: ‎02-09-2017

Re: Message: No debug cores, when trying to use ILA

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Hi @dag1,

 

It looks like your clock is not connected to anything because your buffers are declared as asynchronous (they don't really depend of any clock). It's a good practice to always have these type of registers in sync with a clock. Id addition, the ILA expects to use the same clock that is being used in the logic, so since you don't have any clock being used, it can't find any either.

I suggest you modify your VHDL to have the registers be synchronized with the input clock. You should be able to just modify your code to have something like:

 

process (clk100mhz)
begin
    if rising_edge(clk100mhz) then
        s <= x xor y;
        c <= x and y;
    end if;
end process;

At that point, once you synthesize it, since now the update of the s and c outputs depend of the clk100mhz rising edge, Vivado will make that clock available for you in the Setup Debug window and you should be able to finalize the ILA insertion.

Thanks,

 

Andre Guerrero

Product Applications Engineer

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Explorer
Explorer
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Registered: ‎12-08-2007

Re: Message: No debug cores, when trying to use ILA

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As you know, a Half Adder is a combinational circuit, not a sequential one (no clock).

I added the clock (and not connected it) because that would change the behavior of the Half Adder.

Before I try your suggestion, I want to understand something basic about the Vivado: Combinational circuits cannot be debugged by the ILA IP ?

 

 

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Moderator
Moderator
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Registered: ‎02-09-2017

Re: Message: No debug cores, when trying to use ILA

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Hi @dag1,

 

I grabbed the VHDL code that you shared in your first message to make a test and confirmation. If you are using the Set Up Debug method, Vivado will not allow you to insert and ILA to monitor purely combination circuits. That's because the Set Up Debug "algorithm" is to look into the nets you are trying to connect to the ILA and try to use the same clock domain to clock the ILA. Since it detects that those probes have no clock domain at all, the ILA doesn't even get inserted.

So that's a good lesson!

For such cases, you'll need to go with the traditional VHDL/Verilog code. You were already doing so in the beginning. 

Here's how I tested it and got it to work:

I created the ILA IP with the IP Catalog, then grabbed your VHDL code and declared the ILA in it (pretty much the way you had it in the beginning). I modified the clock name, and inserted the IBUFDS, but that's just so I could use the differential clock in my test board.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

Library UNISIM;
use UNISIM.vcomponents.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity half_adder is
    Port ( x : in STD_LOGIC;
           y : in STD_LOGIC;
           SYSCLK_P : in STD_LOGIC;
           SYSCLK_N : in STD_LOGIC;
           s : buffer  STD_LOGIC; -- we need buffer in order to read it for ILA
           c : buffer  STD_LOGIC);
end half_adder;

architecture Behavioral of half_adder is

signal clk_in : STD_LOGIC;

component IBUFDS
port(I: in STD_LOGIC; IB: in STD_LOGIC; O: out STD_LOGIC);
end component;

component ila_0
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
    probe1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END component;

begin

IBUFDS_1:IBUFDS port map(
I => SYSCLK_P,
IB => SYSCLK_N,
O => clk_in   
);

MYILA: ila_0 PORT map (clk => clk_in, probe0(1) => x, probe0(0) => y, probe1(1) => s, probe1(0) =>c);

s <= x xor y;
c <= x and y;

end Behavioral;

Up to the RTL elaborated design, we can see that the ILA is in there:

ILA_present_elaborated_Design.JPG

 

In the XDC file, I declared my new clock (I used a 75MHz differential clock), assigned input buttons to x and y, and output LEDs to c and s, so I could physically test in my board:

 

#CLK_74_25 74.25 MHz U69 SI5341B
set_property IOSTANDARD LVDS_25 [get_ports SYSCLK_N]
set_property PACKAGE_PIN AK15 [get_ports SYSCLK_P]
set_property PACKAGE_PIN AK14 [get_ports SYSCLK_N]
set_property IOSTANDARD LVDS_25 [get_ports SYSCLK_P]

create_clock -period 13.460 -name clk_in -add [get_ports SYSCLK_P]

#GPIO
#PUSHBUTTON SWITCHES
set_property PACKAGE_PIN AE15 [get_ports x]
set_property IOSTANDARD LVCMOS33 [get_ports x]
set_property PACKAGE_PIN AG15 [get_ports y]
set_property IOSTANDARD LVCMOS33 [get_ports y]

#GPIO LEDs
set_property PACKAGE_PIN AG14 [get_ports s]
set_property IOSTANDARD LVCMOS33 [get_ports s]
set_property PACKAGE_PIN AF13 [get_ports c]
set_property IOSTANDARD LVCMOS33 [get_ports c]

 

I ran synthesis and Implementation, and checked the schematic after Implementation. The ILA is still there:

ILA_after_implementation.JPG

I finally generated the bitstream and programmed the board, and the ILA pops up and works as expected. In the image below, I created a trigger condition for when X and Y are 1. Observe that the ILA correctly triggered when p_0_in and p_1_in (corresponding buttons for X and Y) where pressed to 1.

ILA_triggered.JPG

 

So the conclusion is, although I initially told you to use the Set Up Debug method because it's easier ( and it is), in your case, since none of the signals being monitored are associated with a clock domain, you really have to do the IP creation with IP Catalog, and subsequently instantiation of the ILA in VHDL.

I hope this helps you.

Thanks,

 

Andre Guerrero

Product Applications Engineer

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Explorer
Explorer
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Registered: ‎12-08-2007

Re: Message: No debug cores, when trying to use ILA

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Thanks for your detailed response.

I created a new project with a new name. The same board as before, Basys3 with the XDC file:

 

## This file is a general .xdc for the Basys3 rev B board
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project

# Clock signal
set_property PACKAGE_PIN W5 [get_ports CLK100MHZ]
set_property IOSTANDARD LVCMOS33 [get_ports CLK100MHZ]

# Switches
#set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
set_property PACKAGE_PIN V17 [get_ports x]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports x]
#set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]

set_property PACKAGE_PIN V16 [get_ports y]
set_property IOSTANDARD LVCMOS33 [get_ports y]

# LEDs
#set_property PACKAGE_PIN U16 [get_ports {LED[0]}]
#	set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}]
#set_property PACKAGE_PIN E19 [get_ports {LED[1]}]
#	set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}]

set_property PACKAGE_PIN U16 [get_ports s]
set_property IOSTANDARD LVCMOS33 [get_ports s]
set_property PACKAGE_PIN E19 [get_ports c]
set_property IOSTANDARD LVCMOS33 [get_ports c]

 

 

I have in my main.vhd the following code:

 

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 12/29/2018 12:02:52 PM
-- Design Name: 
-- Module Name: main - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main is
    Port ( clk100mhz: in std_logic; -- for the ILA
    
           x : in STD_LOGIC;
           y : in STD_LOGIC;
           s : buffer  STD_LOGIC; -- we need buffer in order to read it for ILA
           c : buffer  STD_LOGIC);
end main;

architecture Behavioral of main is

component ila_0
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
    probe1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END component;

begin

MYILA: ila_0 PORT map (clk => clk100mhz, probe0(1) => x, probe0(0) => y, probe1(1) => s, probe1(0) =>c);


s <= x xor y;
c <= x and y;

end Behavioral;

 

 

 

As you did, I also avoided doing the Set up Debug.

 

In the schematic of elaborated design and in the schematic of Synthesized design I see the ILA core with the "green" marks that indicate the debug points. See attached pictures.

Screen Shot 2019-02-04 at 23.44.29.png

Screen Shot 2019-02-04 at 23.51.07.png

 

After running Implementation, and Generate bitstream it fails. I get the following errors:

 

Screen Shot 2019-02-04 at 23.47.09.png

I am not sure why I get a critical warning in the synthesis regarding set_property.

And I am not sure what the meaning of the 3 errors from the write bit stream.

But when I set the option of the following .TCL file in the bit stream generation the error disappears:

 

set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

 

 

I Program the FPGA succesfully (I test it manually by playing with the switches on the board and seeing the LEDs light up correctly).

However, I receive the following error mesage hence I still cannot use the ILA:

 

 

 

WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'MYILA' at location 'uuid_F4C0A3AE563B5DB991F2633901C66BC3' from probes file, since it cannot be found on the programmed device.

 

How am I supposed to check the following (point #1 above)?

Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active

 

I do verify point #2:

 I check the HArdware Device Properties: I see 

BSCAN_SWITCH_USER_MASK = 0001

which is the same as the value reported by 

get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]

 

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Moderator
Moderator
1,114 Views
Registered: ‎02-09-2017

Re: Message: No debug cores, when trying to use ILA

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Hi @dag1,

The problem is still that your ILA/dbg_hub cannot find the clock input.

I think I know why that's happening. First, you should note demote the DRC errors to warnings, you really have to fix those issues.

The DRC I am seeing is saying that the port clk100mhz is both unsconstrained (no pin placement) and does not have an electrical standard assigned to it.

Looking at your XDC file, I can see that those two constraints are there, but guess what? They are declared with capital letters (CLK100MHZ), while in your top file you have declared it with lower case letters (clk100mhz).

I'm pretty sure that Vivado is not finding those ports because the naming is case sensitive.

Please make a test, open your Sytmehsized design and run the following two commands:

get_ports {CLK100MHZ}
get_ports {clk100mhz}

See which ones returns a Null and which one returns an Object (I'm pretty sure the clk100mhz will be the one not Null).

change your XDC constraint to reflect the correct naming and run the Implementation again. That should make the DRC error go away and also get the ILA to receive it's clock.

Thanks,

Andre Guerrero

Product Applications Engineer

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Explorer
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Registered: ‎12-08-2007

Re: Message: No debug cores, when trying to use ILA

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Here is the output from the two commands:

 

get_ports {CLK100MHZ}
WARNING: [Vivado 12-584] No ports matched 'CLK100MHZ'.
get_ports {clk100mhz}
clk100mhz

So you are right.

 

I reran implementation after chaning the XDC clock pin to lower case as you suggested.

And now I can see the ILA's window come up.

thanks very much for your assistance.

Just a small note: If I may input a recommendation to Xilinx, I would say that for engineers writing VHDL code (a case-insensitive language) it would be more "natural" to have Vivado's configuration files, in partuclar the XDC file, not be case-sensitive.