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Visitor chirawat.not
Visitor
10,631 Views
Registered: ‎02-04-2014

Newbie to Chip Scope need help about signal name in Chip Scope

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Hello,

 

I'm newbie to Chip Scope and I need your help about how to select signal in Chip Scope,

after my code are synthesised I cannot see the old name from one in VHDL code. I know the signal name in VHDL code but I don't know the signal name in such Chip Scope shows me. 

 

please give me some advice,

 

Nott

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1 Solution

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Xilinx Employee
Xilinx Employee
18,484 Views
Registered: ‎07-23-2012

Re: Newbie to Chip Scope need help about signal name in Chip Scope

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Please set "Keep Hierarchy" to "Yes" in Synthesis options. It will help you find the signals as per your HDL.
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Scholar pratham
Scholar
10,629 Views
Registered: ‎06-05-2013

Re: Newbie to Chip Scope need help about signal name in Chip Scope

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You should use the keep constraint.

 

Take a  look at the below AR

 

http://www.xilinx.com/support/answers/44464.html

 

For chsipscope you can refer this user guide

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/chipscope_pro_sw_cores_ug029.pdf

-Pratham

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Xilinx Employee
Xilinx Employee
18,485 Views
Registered: ‎07-23-2012

Re: Newbie to Chip Scope need help about signal name in Chip Scope

Jump to solution
Please set "Keep Hierarchy" to "Yes" in Synthesis options. It will help you find the signals as per your HDL.
-----------------------------------------------------------------------------------------------
Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

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Visitor chirawat.not
Visitor
10,591 Views
Registered: ‎02-04-2014

Re: Newbie to Chip Scope need help about signal name in Chip Scope

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Thanks Prathum and Smarell a lot,

 

Smarell, your solution is work. Thanks

 

 

-- Nott

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