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Visitor
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Registered: ‎11-06-2011

No multiple match units for a given trigger port displayed in chipscope

Hello,

 

I am using Spartan 3 (XC3S5000) device. When i insert chipscope using chipscope inserter, i double click  .cdc file in project, and choose the trigger ports and match ports. In the GUI i have chosen no. of trigger ports to be 1, no. of match ports to be 2, trigger width to be 8 bits. However when i implement the ILA core in the device and programme the FPGA using the generated bit file, the chipscope window shows match ports for trigger port0 as M0 only! I expect trigger port0 should have both match units M0 and M1.

When i check the core info the following is displayed:

 

core version:v10.10

coregen version:1.02a

Sample Buffer depth: 512

Data sample width:8 bits

No of trigger ports:1

Has trigger sequencer: no

Has storage qualification: yes

triggerport0: Number of match units:1 (M0)

M0  width: 8 bits

M0 type: basic

M0: no counter

 

 

I am not able to figure out, when i am choosing number of match ports to be 2 in GUI of chipscope ILA inserter, then why only one match port ( i.e M0 for triggerport0) is getting displayed on running" analyze using chipscope" ?

 Any suggestion would help me in understanding the problem.

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