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Adventurer
Adventurer
344 Views
Registered: ‎05-18-2018

OSERDESE3 outputs debuggable in Vivado 2019.1?

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I am trying to view the output of an OSERDESE3 block with ILA probes in Vivado 2019.1 on a Zynq US+ SoC.  When I place the debug probe on the node shown below, implementation errors out because the node is "partially routed". When the debug probe is NOT attached, no such error occurs.

Are OSERDESE3 outputs off-limits for ILA probes? If so, is there some other recommended way to view the signal some in ILA?

2019-09-03 14_38_10-flex - [C__flex14_flex_flex.xpr] - Vivado 2019.1.png

 

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Moderator
Moderator
186 Views
Registered: ‎02-09-2017

Re: OSERDESE3 outputs debuggable in Vivado 2019.1?

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Hi @joelschad,

 

That is correct. The workaround would be to either have the ILA before the OSERDES3 (which I know is going to give you a different waveform, but it could be extrapolated to verify if the rest of the design is working properly) or to use an external oscilloscope to probe the FPGA pins.

Thanks,

Andre Guerrero

Product Applications Engineer

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6 Replies
Xilinx Employee
Xilinx Employee
308 Views
Registered: ‎05-08-2012

Re: OSERDESE3 outputs debuggable in Vivado 2019.1?

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Hi @joelschad 

In this case, you would need to probe on the input side of the OSERDES. The OSERDES to OBUFDS is a dedicated connection, so adding another connection physically would not be able to route.


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Adventurer
Adventurer
293 Views
Registered: ‎05-18-2018

Re: OSERDESE3 outputs debuggable in Vivado 2019.1?

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Thanks, marcb.

Are all OSERDESE3 OQ outputs off-limits for ILA probes, or just when they're connecting OSERDESE3 to OBUFDS?

Is this restriction of probe placement called out by a specific name in the User Guides so I can avoid fighting this problem in the future with other blocks?

 

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Moderator
Moderator
220 Views
Registered: ‎02-09-2017

Re: OSERDESE3 outputs debuggable in Vivado 2019.1?

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HI @joelschad,

The restriction about OSERDES3 is always true.

This is the expected behavior and the issues stems from the fact that the ODDRE/OSERDES is placed in the IOB pad, where the ILA is physically not capable of reaching.

Basically, the components which cannot be connected to the ILA are the ones placed in the IOB pad, as described in the image below and in the document UltraScale Architecture SelectIO Resources - UG571, pg.16. In addition, ODDRs are commonly converted into OSERDES by Vivado, so that component is also not allowed.

UG571_IOPAD.PNG

Thanks,

Andre Guerrero

Product Applications Engineer

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Adventurer
Adventurer
199 Views
Registered: ‎05-18-2018

Re: OSERDESE3 outputs debuggable in Vivado 2019.1?

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Thanks - very helpful.

So am I correct in saying that there is no practical way using Vivado's debug tools to see the outputs of an OSERDESE3 block, and no workaround, because these IOB pads are at the fabric's edge?

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Moderator
Moderator
187 Views
Registered: ‎02-09-2017

Re: OSERDESE3 outputs debuggable in Vivado 2019.1?

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Hi @joelschad,

 

That is correct. The workaround would be to either have the ILA before the OSERDES3 (which I know is going to give you a different waveform, but it could be extrapolated to verify if the rest of the design is working properly) or to use an external oscilloscope to probe the FPGA pins.

Thanks,

Andre Guerrero

Product Applications Engineer

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Adventurer
Adventurer
167 Views
Registered: ‎05-18-2018

Re: OSERDESE3 outputs debuggable in Vivado 2019.1?

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Thank you for clarifying.
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