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Scholar helmutforren
Scholar
15,067 Views
Registered: ‎06-23-2014

Please help me stop beating my head against the wall

I got a little further on http://forums.xilinx.com/t5/Design-Tools-Others/Increase-ChipScope-Pro-Window-Depth/td-p/501616

 

I found http://fileadmin.cs.lth.se/cs/Education/EDA385/HT10/documents/KaziChipScopeTutorial.pdf that gave advice to run menu option Debug / Debug Configuration from Platform Studio.  I did this and changed max samples from 1024 to 2048.

 

Now, in Chipscope, I can select 2048 samples rather than only 1024.

 

But now triggering no longer works.  I must still be missing some integration step.  But I can find no doc other than what I've mentioned, and it doesn't cover my specific case.  Is there any actually USEFUL doc out there that's APPLICABLE to triggering on a GPIO value and capturing a buffer content, as was done with the reference design I'm working from (Avnet Maximum ADC DAC)?

 

Does anybody out there know how to use ChipScope with SDK?

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7 Replies
Scholar dwisehart
Scholar
15,066 Views
Registered: ‎06-23-2013

Re: Please help me stop beating my head against the wall

Were there any warnings during the implementation that mention ILA?

 

Daniel

 

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Scholar helmutforren
Scholar
15,060 Views
Registered: ‎06-23-2014

Re: Please help me stop beating my head against the wall

Thanks for helping.

 

No, I don't believe so.  Of course, I don't know what "during implementation" really means.  Too much new jargon.  

 

(((Correction.  I've re-run everything.  To get there quicker, see "ILA ERRORS" far below.)))

 

With that said, when from Platform Studio I *revisit* menu option Debug / Debug Configuration, and then also *revist* chipscope_ila_0, and then click "OK"...  some process runs and spits out the warnings below.  The text "ILA" doesn't occur anywhere in these warnings.

 

WARNING:EDK:4088 - IPNAME: microblaze, INSTANCE: microblaze_0 - Superseded core for architecture 'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 31 
WARNING:EDK:4088 - IPNAME: lmb_v10, INSTANCE: ilmb - Superseded core for architecture 'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 54 
WARNING:EDK:4088 - IPNAME: lmb_v10, INSTANCE: dlmb - Superseded core for architecture 'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 61 
WARNING:EDK:4088 - IPNAME: lmb_bram_if_cntlr, INSTANCE: dlmb_cntlr - Superseded core for architecture 'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 68 
WARNING:EDK:4088 - IPNAME: lmb_bram_if_cntlr, INSTANCE: ilmb_cntlr - Superseded core for architecture 'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 77 
WARNING:EDK:4088 - IPNAME: mdm, INSTANCE: mdm_0 - Superseded core for architecture 'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 174 
WARNING:EDK:4088 - IPNAME: proc_sys_reset, INSTANCE: proc_sys_reset_0 - Superseded core for architecture 'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 187 
WARNING:EDK:4088 - IPNAME: microblaze, INSTANCE: microblaze_0 - Superseded core for architecture 'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 31 
WARNING:EDK:4088 - IPNAME: lmb_v10, INSTANCE: ilmb - Superseded core for architecture 'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 54 
WARNING:EDK:4088 - IPNAME: lmb_v10, INSTANCE: dlmb - Superseded core for architecture 'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 61 
WARNING:EDK:4088 - IPNAME: lmb_bram_if_cntlr, INSTANCE: dlmb_cntlr - Superseded core for architecture 'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 68 
WARNING:EDK:4088 - IPNAME: lmb_bram_if_cntlr, INSTANCE: ilmb_cntlr - Superseded core for architecture 'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 77 
WARNING:EDK:4088 - IPNAME: mdm, INSTANCE: mdm_0 - Superseded core for architecture 'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 174 
WARNING:EDK:4088 - IPNAME: proc_sys_reset, INSTANCE: proc_sys_reset_0 - Superseded core for architecture 'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 187 

 Note that this reference design was originaled in ISE Design Studio 12.2.  I opened it in 14.7.  It gave messages about upgrading, so I thought it would have upgraded all the things.  Anyway, this may have NOTHING to do with my bottom line difficulty.  Or it may have everything to do with it.

 

Next:  From Platform Studio when I select menu option Project / Export Hardware Design to SDK..., I get these warnings below.  The text "ILA" doesn't occur anywhere in these warnings.

 

WARNING:EDK:4088 - IPNAME: microblaze, INSTANCE: microblaze_0 - Superseded core
   for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 31 
WARNING:EDK:4088 - IPNAME: lmb_v10, INSTANCE: ilmb - Superseded core for
   architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 54 
WARNING:EDK:4088 - IPNAME: lmb_v10, INSTANCE: dlmb - Superseded core for
   architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 61 
WARNING:EDK:4088 - IPNAME: lmb_bram_if_cntlr, INSTANCE: dlmb_cntlr - Superseded
   core for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 68 
WARNING:EDK:4088 - IPNAME: lmb_bram_if_cntlr, INSTANCE: ilmb_cntlr - Superseded
   core for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 77 
WARNING:EDK:4088 - IPNAME: mdm, INSTANCE: mdm_0 - Superseded core for
   architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 174 
WARNING:EDK:4088 - IPNAME: proc_sys_reset, INSTANCE: proc_sys_reset_0 -
   Superseded core for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 187 
WARNING:EDK:4088 - IPNAME: microblaze, INSTANCE: microblaze_0 - Superseded core
   for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 31 
WARNING:EDK:4088 - IPNAME: lmb_v10, INSTANCE: ilmb - Superseded core for
   architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 54 
WARNING:EDK:4088 - IPNAME: lmb_v10, INSTANCE: dlmb - Superseded core for
   architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 61 
WARNING:EDK:4088 - IPNAME: lmb_bram_if_cntlr, INSTANCE: dlmb_cntlr - Superseded
   core for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 68 
WARNING:EDK:4088 - IPNAME: lmb_bram_if_cntlr, INSTANCE: ilmb_cntlr - Superseded
   core for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 77 
WARNING:EDK:4088 - IPNAME: mdm, INSTANCE: mdm_0 - Superseded core for
   architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 174 
WARNING:EDK:4088 - IPNAME: proc_sys_reset, INSTANCE: proc_sys_reset_0 -
   Superseded core for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 187 
WARNING:EDK:4180 - PORT: IWAIT, CONNECTOR: ilmb_LMB_Wait - No driver found. Port
   will be driven to GND -
   M:\Xilinx\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_30_b\d
   ata\microblaze_v2_1_0.mpd line 241 
WARNING:EDK:4180 - PORT: DWAIT, CONNECTOR: dlmb_LMB_Wait - No driver found. Port
   will be driven to GND -
   M:\Xilinx\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_30_b\d
   ata\microblaze_v2_1_0.mpd line 277 
WARNING:EDK:4181 - PORT: Peripheral_Reset, CONNECTOR: sys_periph_reset -
   floating connection -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 197 
WARNING:EDK:4088 - IPNAME: microblaze, INSTANCE: microblaze_0 - Superseded core
   for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 31 
WARNING:EDK:4088 - IPNAME: lmb_v10, INSTANCE: ilmb - Superseded core for
   architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 54 
WARNING:EDK:4088 - IPNAME: lmb_v10, INSTANCE: dlmb - Superseded core for
   architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 61 
WARNING:EDK:4088 - IPNAME: lmb_bram_if_cntlr, INSTANCE: dlmb_cntlr - Superseded
   core for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 68 
WARNING:EDK:4088 - IPNAME: lmb_bram_if_cntlr, INSTANCE: ilmb_cntlr - Superseded
   core for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 77 
WARNING:EDK:4088 - IPNAME: mdm, INSTANCE: mdm_0 - Superseded core for
   architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 174 
WARNING:EDK:4088 - IPNAME: proc_sys_reset, INSTANCE: proc_sys_reset_0 -
   Superseded core for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 187 
WARNING:EDK:878 - Could not find IP doc
   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=plb_v46;v=v1_05_a;d=plb_v46.pdf
WARNING:EDK:878 - Could not find IP doc
   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=bram_block;v=v1_00_a;d=bram_block.
   pdf
WARNING:EDK:878 - Could not find IP doc
   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=xps_uartlite;v=v1_02_a;d=xps_uartl
   ite.pdf
WARNING:EDK:878 - Could not find IP doc
   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=xps_gpio;v=v2_00_a;d=xps_gpio.pdf
WARNING:EDK:878 - Could not find IP doc
   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=xps_gpio;v=v2_00_a;d=xps_gpio.pdf
WARNING:EDK:878 - Could not find IP doc
   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=xps_gpio;v=v2_00_a;d=xps_gpio.pdf
WARNING:EDK:878 - Could not find IP doc
   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=xps_timer;v=v1_02_a;d=xps_timer.pd
   f
WARNING:EDK:878 - Could not find IP doc
   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=clock_generator;v=v4_03_a;d=clock_
   generator.pdf
WARNING:EDK:878 - Could not find IP doc
   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=xps_intc;v=v2_01_a;d=xps_intc.pdf
WARNING:EDK:878 - Could not find IP doc
   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=xps_iic;v=v2_03_a;d=xps_iic.pdf
WARNING:EDK:878 - Could not find IP doc
   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=xps_spi;v=v2_02_a;d=xps_spi.pdf
WARNING:EDK:878 - Could not find IP doc
   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=xps_bram_if_cntlr;v=v1_00_b;d=xps_
   bram_if_cntlr.pdf
WARNING:EDK:878 - Could not find IP doc
   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=bram_block;v=v1_00_a;d=bram_block.
   pdf
WARNING:EDK:878 - Could not find IP doc
   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=xps_bram_if_cntlr;v=v1_00_b;d=xps_
   bram_if_cntlr.pdf
WARNING:EDK:878 - Could not find IP doc
   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=bram_block;v=v1_00_a;d=bram_block.
   pdf

 

Next, back in ISE Project Navigator, when I select my top.vhd and double click on Generate Programming File, I get the following warnings that *DO* include references to "ila".

 

ILA ERRORS: See below.  I don't know what they mean.

 

WARNING:EDK - IPNAME: microblaze, INSTANCE: microblaze_0 - Superseded core for
   architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 31 
WARNING:EDK - IPNAME: lmb_v10, INSTANCE: ilmb - Superseded core for architecture
   'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs
   line 54 
WARNING:EDK - IPNAME: lmb_v10, INSTANCE: dlmb - Superseded core for architecture
   'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs
   line 61 
WARNING:EDK - IPNAME: lmb_bram_if_cntlr, INSTANCE: dlmb_cntlr - Superseded core
   for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 68 
WARNING:EDK - IPNAME: lmb_bram_if_cntlr, INSTANCE: ilmb_cntlr - Superseded core
   for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 77 
WARNING:EDK - IPNAME: mdm, INSTANCE: mdm_0 - Superseded core for architecture
   'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs
   line 174 
WARNING:EDK - IPNAME: proc_sys_reset, INSTANCE: proc_sys_reset_0 - Superseded
   core for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 187 
WARNING:EDK - IPNAME: microblaze, INSTANCE: microblaze_0 - Superseded core for
   architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 31 
WARNING:EDK - IPNAME: lmb_v10, INSTANCE: ilmb - Superseded core for architecture
   'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs
   line 54 
WARNING:EDK - IPNAME: lmb_v10, INSTANCE: dlmb - Superseded core for architecture
   'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs
   line 61 
WARNING:EDK - IPNAME: lmb_bram_if_cntlr, INSTANCE: dlmb_cntlr - Superseded core
   for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 68 
WARNING:EDK - IPNAME: lmb_bram_if_cntlr, INSTANCE: ilmb_cntlr - Superseded core
   for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 77 
WARNING:EDK - IPNAME: mdm, INSTANCE: mdm_0 - Superseded core for architecture
   'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs
   line 174 
WARNING:EDK - IPNAME: proc_sys_reset, INSTANCE: proc_sys_reset_0 - Superseded
   core for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 187 
WARNING:EDK:4088 - IPNAME: microblaze, INSTANCE: microblaze_0 - Superseded core
   for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 31 
WARNING:EDK:4088 - IPNAME: lmb_v10, INSTANCE: ilmb - Superseded core for
   architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 54 
WARNING:EDK:4088 - IPNAME: lmb_v10, INSTANCE: dlmb - Superseded core for
   architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 61 
WARNING:EDK:4088 - IPNAME: lmb_bram_if_cntlr, INSTANCE: dlmb_cntlr - Superseded
   core for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 68 
WARNING:EDK:4088 - IPNAME: lmb_bram_if_cntlr, INSTANCE: ilmb_cntlr - Superseded
   core for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 77 
WARNING:EDK:4088 - IPNAME: mdm, INSTANCE: mdm_0 - Superseded core for
   architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 174 
WARNING:EDK:4088 - IPNAME: proc_sys_reset, INSTANCE: proc_sys_reset_0 -
   Superseded core for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 187 
WARNING:EDK:4088 - IPNAME: microblaze, INSTANCE: microblaze_0 - Superseded core
   for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 31 
WARNING:EDK:4088 - IPNAME: lmb_v10, INSTANCE: ilmb - Superseded core for
   architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 54 
WARNING:EDK:4088 - IPNAME: lmb_v10, INSTANCE: dlmb - Superseded core for
   architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 61 
WARNING:EDK:4088 - IPNAME: lmb_bram_if_cntlr, INSTANCE: dlmb_cntlr - Superseded
   core for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 68 
WARNING:EDK:4088 - IPNAME: lmb_bram_if_cntlr, INSTANCE: ilmb_cntlr - Superseded
   core for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 77 
WARNING:EDK:4088 - IPNAME: mdm, INSTANCE: mdm_0 - Superseded core for
   architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 174 
WARNING:EDK:4088 - IPNAME: proc_sys_reset, INSTANCE: proc_sys_reset_0 -
   Superseded core for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 187 
WARNING:EDK:4180 - PORT: IWAIT, CONNECTOR: ilmb_LMB_Wait - No driver found. Port
   will be driven to GND -
   M:\Xilinx\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_30_b\d
   ata\microblaze_v2_1_0.mpd line 241 
WARNING:EDK:4180 - PORT: DWAIT, CONNECTOR: dlmb_LMB_Wait - No driver found. Port
   will be driven to GND -
   M:\Xilinx\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_30_b\d
   ata\microblaze_v2_1_0.mpd line 277 
WARNING:EDK:4181 - PORT: Peripheral_Reset, CONNECTOR: sys_periph_reset -
   floating connection -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 197 
WARNING:ConstraintSystem:192 - The TNM 'D2_CLK', does not directly or indirectly
   drive any flip-flops, latches and/or RAMS and cannot be actively used by the
   referencing TIg constraint ''. If clock manager blocks are directly or
   indirectly driven, a new TNM constraint will not be derived since the none of
   the referencing constraints are a PERIOD constraint. This TNM is used in the
   following user groups and/or specifications:
   <TIMESPEC TS_D2_TO_T2 = FROM D2_CLK TO "FFS" TIG;>
   [M:\Night-Sky\Src\RefDesign_14_7_BigBuf\TopLevel\system/system_chipscope_ila_
   0_wrapper.ncf(6)]
   <TIMESPEC TS_J2_TO_D2 = FROM "FFS" TO D2_CLK TIG;>
   [M:\Night-Sky\Src\RefDesign_14_7_BigBuf\TopLevel\system/system_chipscope_ila_
   0_wrapper.ncf(7)]
   <TIMESPEC TS_J3_TO_D2 = FROM "FFS" TO D2_CLK TIG;>
   [M:\Night-Sky\Src\RefDesign_14_7_BigBuf\TopLevel\system/system_chipscope_ila_
   0_wrapper.ncf(8)]
   <TIMESPEC TS_J4_TO_D2 = FROM "FFS" TO D2_CLK TIG;>
WARNING:ConstraintSystem:197 - The following specification is invalid because
   the referenced TNM constraint was removed:
   <TIMESPEC TS_D2_TO_T2 = FROM D2_CLK TO "FFS" TIG;>
   [M:\Night-Sky\Src\RefDesign_14_7_BigBuf\TopLevel\system/system_chipscope_ila_
   0_wrapper.ncf(6)]
WARNING:ConstraintSystem:197 - The following specification is invalid because
   the referenced TNM constraint was removed:
   <TIMESPEC TS_J2_TO_D2 = FROM "FFS" TO D2_CLK TIG;>
   [M:\Night-Sky\Src\RefDesign_14_7_BigBuf\TopLevel\system/system_chipscope_ila_
   0_wrapper.ncf(7)]
WARNING:ConstraintSystem:197 - The following specification is invalid because
   the referenced TNM constraint was removed:
   <TIMESPEC TS_J3_TO_D2 = FROM "FFS" TO D2_CLK TIG;>
   [M:\Night-Sky\Src\RefDesign_14_7_BigBuf\TopLevel\system/system_chipscope_ila_
   0_wrapper.ncf(8)]
WARNING:ConstraintSystem:197 - The following specification is invalid because
   the referenced TNM constraint was removed:
   <TIMESPEC TS_J4_TO_D2 = FROM "FFS" TO D2_CLK TIG;>
   [M:\Night-Sky\Src\RefDesign_14_7_BigBuf\TopLevel\system/system_chipscope_ila_
   0_wrapper.ncf(9)]
WARNING:ConstraintSystem:190 - The TNM 'J_CLK', does not directly or indirectly
   drive any flip-flops, latches and/or RAMS and cannot be actively used by the
   referencing Period constraint 'TS_J_CLK'. If clock manager blocks are
   directly or indirectly driven, a new TNM and PERIOD are derived only if the
   PERIOD constraint is the only referencing constraint and if an output of the
   clock manager block drives flip-flops, latches or RAMs.  
   This TNM is used in the following user groups and/or specifications:
   <TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;>
   [M:\Night-Sky\Src\RefDesign_14_7_BigBuf\TopLevel\system/system_chipscope_icon
   _0_wrapper.ncf(2)]
   <TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;>
   [M:\Night-Sky\Src\RefDesign_14_7_BigBuf\TopLevel\system/system_chipscope_icon
   _0_wrapper.ncf(6)]
   <TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;>
   [M:\Night-Sky\Src\RefDesign_14_7_BigBuf\TopLevel\system/system_chipscope_icon
   _0_wrapper.ncf(8)]
WARNING:ConstraintSystem:197 - The following specification is invalid because
   the referenced TNM constraint was removed:
   <TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;>
   [M:\Night-Sky\Src\RefDesign_14_7_BigBuf\TopLevel\system/system_chipscope_icon
   _0_wrapper.ncf(2)]
WARNING:ConstraintSystem:197 - The following specification is invalid because
   the referenced TNM constraint was removed:
   <TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;>
   [M:\Night-Sky\Src\RefDesign_14_7_BigBuf\TopLevel\system/system_chipscope_icon
   _0_wrapper.ncf(6)]
WARNING:ConstraintSystem:197 - The following specification is invalid because
   the referenced TNM constraint was removed:
   <TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;>
   [M:\Night-Sky\Src\RefDesign_14_7_BigBuf\TopLevel\system/system_chipscope_icon
   _0_wrapper.ncf(8)]
WARNING:ConstraintSystem:197 - The following specification is invalid because
   the referenced TNM constraint was removed:
   <TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;>
   [M:\Night-Sky\Src\RefDesign_14_7_BigBuf\TopLevel\system/system_chipscope_icon
   _0_wrapper.ncf(9)]
WARNING:ConstraintSystem:192 - The TNM 'U_CLK', does not directly or indirectly
   drive any flip-flops, latches and/or RAMS and cannot be actively used by the
   referencing MaxDelay constraint 'TS_U_TO_J'. If clock manager blocks are
   directly or indirectly driven, a new TNM constraint will not be derived since
   the none of the referencing constraints are a PERIOD constraint. This TNM is
   used in the following user groups and/or specifications:
   <TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;>
   [M:\Night-Sky\Src\RefDesign_14_7_BigBuf\TopLevel\system/system_chipscope_icon
   _0_wrapper.ncf(6)]
   <TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;>
   [M:\Night-Sky\Src\RefDesign_14_7_BigBuf\TopLevel\system/system_chipscope_icon
   _0_wrapper.ncf(7)]
WARNING:ConstraintSystem:197 - The following specification is invalid because
   the referenced TNM constraint was removed:
   <TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;>
   [M:\Night-Sky\Src\RefDesign_14_7_BigBuf\TopLevel\system/system_chipscope_icon
   _0_wrapper.ncf(6)]
WARNING:ConstraintSystem:197 - The following specification is invalid because
   the referenced TNM constraint was removed:
   <TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;>
   [M:\Night-Sky\Src\RefDesign_14_7_BigBuf\TopLevel\system/system_chipscope_icon
   _0_wrapper.ncf(7)]
WARNING:NgdBuild:981 - Could not find any associations for the following
   constraint:
WARNING:ConstraintSystem:56 - Constraint <TIMESPEC TS_J_CLK = PERIOD "J_CLK"
   30000.000000000 pS HIGH 50.000000000 %;>: Unable to find an active 'TNM' or
   'TimeGrp' constraint named 'J_CLK'.
WARNING:ConstraintSystem:56 - Constraint <TIMESPEC TS_U_TO_J = FROM "U_CLK" TO
   "J_CLK" 15000.000000000 pS;>: Unable to find an active 'TimeGrp' or 'TNM' or
   'TPSync' constraint named 'U_CLK'.
WARNING:ConstraintSystem:56 - Constraint <TIMESPEC TS_U_TO_J = FROM "U_CLK" TO
   "J_CLK" 15000.000000000 pS;>: Unable to find an active 'TimeGrp' or 'TNM' or
   'TPSync' constraint named 'J_CLK'.
WARNING:ConstraintSystem:56 - Constraint <TIMESPEC TS_U_TO_U = FROM "U_CLK" TO
   "U_CLK" 15000.000000000 pS;>: Unable to find an active 'TimeGrp' or 'TNM' or
   'TPSync' constraint named 'U_CLK'.
WARNING:ConstraintSystem:56 - Constraint <TIMESPEC TS_U_TO_U = FROM "U_CLK" TO
   "U_CLK" 15000.000000000 pS;>: Unable to find an active 'TimeGrp' or 'TNM' or
   'TPSync' constraint named 'U_CLK'.
WARNING:ConstraintSystem:56 - Constraint <TIMESPEC TS_J_TO_D = FROM "J_CLK" TO
   "D_CLK" TIG;>: Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync'
   constraint named 'J_CLK'.
WARNING:ConstraintSystem:56 - Constraint <TIMESPEC TS_D_TO_J = FROM "D_CLK" TO
   "J_CLK" TIG;>: Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync'
   constraint named 'J_CLK'.
WARNING:ConstraintSystem:56 - Constraint <TIMESPEC TS_D2_TO_T2 = FROM "D2_CLK"
   TO FFS TIG;>: Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync'
   constraint named 'D2_CLK'.
WARNING:ConstraintSystem:56 - Constraint <TIMESPEC TS_J2_TO_D2 = FROM FFS TO
   "D2_CLK" TIG;>: Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync'
   constraint named 'D2_CLK'.
WARNING:ConstraintSystem:56 - Constraint <TIMESPEC TS_J3_TO_D2 = FROM FFS TO
   "D2_CLK" TIG;>: Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync'
   constraint named 'D2_CLK'.
WARNING:ConstraintSystem:56 - Constraint <TIMESPEC TS_J4_TO_D2 = FROM FFS TO
   "D2_CLK" TIG;>: Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync'
   constraint named 'D2_CLK'.
WARNING:ConstraintSystem - A target design object for the Locate constraint
   '<NET "xps_spi_0_MOSI_pin" LOC = D8>' could not be found and so the Locate
   constraint will be removed.
WARNING:ConstraintSystem - A target design object for the Locate constraint
   '<NET "xps_spi_0_MISO_pin" LOC = C8>' could not be found and so the Locate
   constraint will be removed.
WARNING:ConstraintSystem - A target design object for the Locate constraint
   '<NET "xps_spi_0_SCK_pin" LOC = D12>' could not be found and so the Locate
   constraint will be removed.
WARNING:ConstraintSystem - A target design object for the Locate constraint
   '<NET "fpga_0_IIC_EEPROM_Scl_pin" LOC = M13>' could not be found and so the
   Locate constraint will be removed.
WARNING:ConstraintSystem - A target design object for the Locate constraint
   '<NET "fpga_0_IIC_EEPROM_Sda_pin" LOC = L14>' could not be found and so the
   Locate constraint will be removed.
WARNING:ConstraintSystem - A target design object for the Locate constraint
   '<NET "xps_spi_0_SS_pin<1>" LOC = C10>' could not be found and so the Locate
   constraint will be removed.
WARNING:ConstraintSystem - A target design object for the Locate constraint
   '<NET "xps_spi_0_SS_pin<0>" LOC = C12>' could not be found and so the Locate
   constraint will be removed.
WARNING:ConstraintSystem - A target design object for the Locate constraint
   '<NET "fpga_0_rst_1_sys_rst_pin_IBUF" LOC = H18>' could not be found and so
   the Locate constraint will be removed.
WARNING:ConstraintSystem - A target design object for the Locate constraint
   '<NET "fpga_0_clk_1_sys_clk_pin_IBUF" LOC = L12>' could not be found and so
   the Locate constraint will be removed.
WARNING:ConstraintSystem - A target design object for the Locate constraint
   '<NET "ADC_DRDYOUT_pin_0_IBUF" LOC = U13>' could not be found and so the
   Locate constraint will be removed.
WARNING:NgdBuild:1345 - The constraint <TIMESPEC TS_sys_clk_pin = PERIOD
   "sys_clk_pin" 66666.000000000 KHz HIGH 50.000000000 %;> is overridden by the
   constraint <TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 66666 kHz;>
   [Top.ucf(14)]. The overriden constraint usually comes from the input netlist
   or ncf files. Please set XIL_NGDBUILD_CONSTR_OVERRIDE_ERROR to promote this
   message to an error.
WARNING:NgdBuild:1012 - The constraint <CONFIG ENABLE_SUSPEND = FILTERED> is
   overridden on the design object Top by the constraint <CONFIG ENABLE_SUSPEND
   = FILTERED;> [Top.ucf(8)].
WARNING:NgdBuild:1012 - The constraint <CONFIG VCCAUX = "2.5"> is overridden on
   the design object Top by the constraint <CONFIG VCCAUX = "2.5" ;>
   [Top.ucf(5)].
WARNING:NgdBuild:1012 - The constraint <NET "xps_spi_0_MOSI_pin" SLEW = SLOW> is
   overridden on the design object xps_spi_0_MOSI_pin by the constraint
   <SLEW=SLOW;> [Top.ucf(24)].
WARNING:NgdBuild:1012 - The constraint <NET "xps_spi_0_MOSI_pin" LOC = D8> is
   overridden on the design object xps_spi_0_MOSI_pin by the constraint <Net
   xps_spi_0_MOSI_pin LOC="D8" |> [Top.ucf(24)].
WARNING:NgdBuild:1012 - The constraint <NET "xps_spi_0_MISO_pin" SLEW = SLOW> is
   overridden on the design object xps_spi_0_MISO_pin by the constraint
   <SLEW=SLOW;> [Top.ucf(23)].
WARNING:NgdBuild:1012 - The constraint <NET "xps_spi_0_MISO_pin" LOC = C8> is
   overridden on the design object xps_spi_0_MISO_pin by the constraint <Net
   xps_spi_0_MISO_pin LOC="C8" |> [Top.ucf(23)].
WARNING:NgdBuild:1012 - The constraint <NET "xps_spi_0_SCK_pin" SLEW = SLOW> is
   overridden on the design object xps_spi_0_SCK_pin by the constraint
   <SLEW=SLOW;> [Top.ucf(22)].
WARNING:NgdBuild:1012 - The constraint <NET "xps_spi_0_SCK_pin" LOC = D12> is
   overridden on the design object xps_spi_0_SCK_pin by the constraint <Net
   xps_spi_0_SCK_pin LOC="D12" |> [Top.ucf(22)].
WARNING:NgdBuild:1012 - The constraint <NET "fpga_0_IIC_EEPROM_Scl_pin"
   IOSTANDARD = "LVCMOS33"> is overridden on the design object
   fpga_0_IIC_EEPROM_Scl_pin by the constraint <IOSTANDARD = LVCMOS33;>
   [Top.ucf(20)].
WARNING:NgdBuild:1012 - The constraint <NET "fpga_0_IIC_EEPROM_Scl_pin" DRIVE =
   6> is overridden on the design object fpga_0_IIC_EEPROM_Scl_pin by the
   constraint <DRIVE=6 |> [Top.ucf(20)].
WARNING:NgdBuild:1012 - The constraint <NET "fpga_0_IIC_EEPROM_Scl_pin" SLEW =
   SLOW> is overridden on the design object fpga_0_IIC_EEPROM_Scl_pin by the
   constraint <SLEW=SLOW  |> [Top.ucf(20)].
WARNING:NgdBuild:1012 - The constraint <NET "fpga_0_IIC_EEPROM_Scl_pin" LOC =
   M13> is overridden on the design object fpga_0_IIC_EEPROM_Scl_pin by the
   constraint <Net fpga_0_IIC_EEPROM_Scl_pin LOC=M13  |> [Top.ucf(20)].
WARNING:NgdBuild:1012 - The constraint <NET "fpga_0_IIC_EEPROM_Sda_pin"
   IOSTANDARD = "LVCMOS33"> is overridden on the design object
   fpga_0_IIC_EEPROM_Sda_pin by the constraint <IOSTANDARD = LVCMOS33;>
   [Top.ucf(19)].
WARNING:NgdBuild:1012 - The constraint <NET "fpga_0_IIC_EEPROM_Sda_pin" DRIVE =
   6> is overridden on the design object fpga_0_IIC_EEPROM_Sda_pin by the
   constraint <DRIVE=6 |> [Top.ucf(19)].
WARNING:NgdBuild:1012 - The constraint <NET "fpga_0_IIC_EEPROM_Sda_pin" SLEW =
   SLOW> is overridden on the design object fpga_0_IIC_EEPROM_Sda_pin by the
   constraint <SLEW=SLOW  |> [Top.ucf(19)].
WARNING:NgdBuild:1012 - The constraint <NET "fpga_0_IIC_EEPROM_Sda_pin" LOC =
   L14> is overridden on the design object fpga_0_IIC_EEPROM_Sda_pin by the
   constraint <Net fpga_0_IIC_EEPROM_Sda_pin LOC=L14  |> [Top.ucf(19)].
WARNING:NgdBuild:1012 - The constraint <NET "xps_spi_0_SS_pin<1>" SLEW = SLOW>
   is overridden on the design object xps_spi_0_SS_pin<1> by the constraint
   <SLEW=SLOW;> [Top.ucf(26)].
WARNING:NgdBuild:1012 - The constraint <NET "xps_spi_0_SS_pin<1>" LOC = C10> is
   overridden on the design object xps_spi_0_SS_pin<1> by the constraint <Net
   xps_spi_0_SS_pin<1> LOC="C10" |> [Top.ucf(26)].
WARNING:NgdBuild:1012 - The constraint <NET "xps_spi_0_SS_pin<0>" SLEW = SLOW>
   is overridden on the design object xps_spi_0_SS_pin<0> by the constraint
   <SLEW=SLOW;> [Top.ucf(25)].
WARNING:NgdBuild:1012 - The constraint <NET "xps_spi_0_SS_pin<0>" LOC = C12> is
   overridden on the design object xps_spi_0_SS_pin<0> by the constraint <Net
   xps_spi_0_SS_pin<0> LOC="C12" |> [Top.ucf(25)].
WARNING:NgdBuild:1012 - The constraint <NET "fpga_0_rst_1_sys_rst_pin_IBUF"
   IOSTANDARD = "LVCMOS33"> is overridden on the design object
   fpga_0_rst_1_sys_rst_pin by the constraint <IOSTANDARD = LVCMOS33;>
   [Top.ucf(17)].
WARNING:NgdBuild:1012 - The constraint <NET "fpga_0_rst_1_sys_rst_pin_IBUF" LOC
   = H18> is overridden on the design object fpga_0_rst_1_sys_rst_pin by the
   constraint <Net fpga_0_rst_1_sys_rst_pin LOC=H18 |> [Top.ucf(17)].
WARNING:NgdBuild:1012 - The constraint <NET "fpga_0_clk_1_sys_clk_pin_IBUF"
   IOSTANDARD = "LVCMOS33"> is overridden on the design object
   fpga_0_clk_1_sys_clk_pin by the constraint <IOSTANDARD = LVCMOS33;>
   [Top.ucf(15)].
WARNING:NgdBuild:1012 - The constraint <NET "fpga_0_clk_1_sys_clk_pin_IBUF" LOC
   = L12> is overridden on the design object fpga_0_clk_1_sys_clk_pin by the
   constraint <LOC=L12 |> [Top.ucf(15)].
WARNING:NgdBuild:1012 - The constraint <NET "ADC_DRDYOUT_pin_0_IBUF" IOSTANDARD
   = "LVCMOS33"> is overridden on the design object ADC_DRDYOUT_pin<0> by the
   constraint <IOSTANDARD = LVCMOS33;> [Top.ucf(12)].
WARNING:NgdBuild:1012 - The constraint <NET "ADC_DRDYOUT_pin_0_IBUF" LOC = U13>
   is overridden on the design object ADC_DRDYOUT_pin<0> by the constraint <Net
   ADC_DRDYOUT_pin<0> LOC=U13  |> [Top.ucf(12)].
WARNING:NgdBuild:1440 - User specified non-default attribute value (15) was
   detected for the CLKIN1_PERIOD attribute on PLL
   "clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst".  This does not
   match the PERIOD constraint value (66666 KHz.).  The uncertainty calculation
   will use the PERIOD constraint value.  This could result in incorrect
   uncertainty calculated for PLL output clocks.
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/microblaze_0/microblaze_0/Performance.Decode_I/Using_FPGA.Gen_Bi
   ts[27].MEM_EX_Result_Inst' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE
   [20].TCSR1_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE
   [19].TCSR1_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE
   [18].TCSR1_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE
   [17].TCSR1_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE
   [16].TCSR1_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE
   [15].TCSR1_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE
   [14].TCSR1_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE
   [13].TCSR1_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE
   [12].TCSR1_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE
   [11].TCSR1_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE
   [10].TCSR1_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE
   [9].TCSR1_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE
   [8].TCSR1_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE
   [7].TCSR1_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE
   [6].TCSR1_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE
   [5].TCSR1_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE
   [4].TCSR1_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE
   [3].TCSR1_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE
   [2].TCSR1_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE
   [1].TCSR1_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE
   [0].TCSR1_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE
   [20].TCSR0_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE
   [19].TCSR0_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE
   [18].TCSR0_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE
   [17].TCSR0_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE
   [16].TCSR0_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE
   [15].TCSR0_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE
   [14].TCSR0_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE
   [13].TCSR0_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE
   [12].TCSR0_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE
   [11].TCSR0_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE
   [10].TCSR0_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE
   [9].TCSR0_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE
   [8].TCSR0_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE
   [7].TCSR0_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE
   [6].TCSR0_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE
   [5].TCSR0_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE
   [4].TCSR0_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE
   [3].TCSR0_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE
   [2].TCSR0_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE
   [1].TCSR0_FF_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'Inst_system/xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE
   [0].TCSR0_FF_I' has unconnected output pin
WARNING:NgdBuild:452 - logical net 'N11' has no driver
WARNING:NgdBuild:452 - logical net 'N12' has no driver
WARNING:NgdBuild:452 - logical net 'N13' has no driver
WARNING:NgdBuild:452 - logical net 'N14' has no driver
WARNING:NgdBuild:452 - logical net 'N15' has no driver
WARNING:NgdBuild:452 - logical net 'N16' has no driver
WARNING:NgdBuild:452 - logical net 'N17' has no driver
WARNING:NgdBuild:452 - logical net 'Inst_system/bscan_tdo1' has no driver
WARNING:NgdBuild:478 - clock net Inst_system/bscan_drck1 with clock driver
   Inst_system/mdm_0/mdm_0/BUFG_DRCK1 drives no clock pins
WARNING:Pack:2549 - The register
   "Inst_system/xps_spi_0/xps_spi_0/I_SPI_MODULE/SPI_TRISTATE_CONTROL_IV" has
   the property IOB=TRUE, but was not packed into the OLOGIC component. The
   output signal for register symbol
   Inst_system/xps_spi_0/xps_spi_0/I_SPI_MODULE/SPI_TRISTATE_CONTROL_IV requires
   general routing to fabric, but the register can only be routed to ILOGIC,
   IODELAY, and IOB.
WARNING:Pack:2549 - The register
   "Inst_system/xps_spi_0/xps_spi_0/I_SPI_MODULE/SPI_TRISTATE_CONTROL_IV" has
   the property IOB=TRUE, but was not packed into the OLOGIC component. The
   output signal for register symbol
   Inst_system/xps_spi_0/xps_spi_0/I_SPI_MODULE/SPI_TRISTATE_CONTROL_IV requires
   general routing to fabric, but the register can only be routed to ILOGIC,
   IODELAY, and IOB.
Finished initial Timing Analysis.  WARNING:Par:288 - The signal
WARNING:Par:288 - The signal
   Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[6].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[9].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[14].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[15].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[5].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[4].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[0].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[11].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[10].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[12].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[2].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[3].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[13].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[8].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[1].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
|e_ila_0_icon_control |              |      | |WARNING:Par:283 - There are 16 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   Inst_system/chipscope_ila_0_icon_control<13> is sourced by a combinatorial
   pin. This is not good design practice. Use the CE pin to control the loading
   of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
   <Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_
   I/Using_LUT6.All_RAM32M[7].ram32m_i_RAMD_D1_O> is incomplete. The signal does
   not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_
   I/Using_LUT6.All_RAM32M[6].ram32m_i_RAMD_D1_O> is incomplete. The signal does
   not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_
   I/Using_LUT6.All_RAM32M[9].ram32m_i_RAMD_D1_O> is incomplete. The signal does
   not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_
   I/Using_LUT6.All_RAM32M[14].ram32m_i_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_
   I/Using_LUT6.All_RAM32M[15].ram32m_i_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_
   I/Using_LUT6.All_RAM32M[5].ram32m_i_RAMD_D1_O> is incomplete. The signal does
   not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_
   I/Using_LUT6.All_RAM32M[4].ram32m_i_RAMD_D1_O> is incomplete. The signal does
   not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_
   I/Using_LUT6.All_RAM32M[0].ram32m_i_RAMD_D1_O> is incomplete. The signal does
   not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_
   I/Using_LUT6.All_RAM32M[11].ram32m_i_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_
   I/Using_LUT6.All_RAM32M[10].ram32m_i_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_
   I/Using_LUT6.All_RAM32M[12].ram32m_i_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_
   I/Using_LUT6.All_RAM32M[2].ram32m_i_RAMD_D1_O> is incomplete. The signal does
   not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_
   I/Using_LUT6.All_RAM32M[3].ram32m_i_RAMD_D1_O> is incomplete. The signal does
   not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_
   I/Using_LUT6.All_RAM32M[13].ram32m_i_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_
   I/Using_LUT6.All_RAM32M[8].ram32m_i_RAMD_D1_O> is incomplete. The signal does
   not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <Inst_system/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_
   I/Using_LUT6.All_RAM32M[1].ram32m_i_RAMD_D1_O> is incomplete. The signal does
   not drive any load pins in the design.
WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration
   on
   block:<Inst_system/chipscope_ila_0/chipscope_ila_0/i_chipscope_ila_0/U0/I_NO_
   D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCAD
   E_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[2].u_ramb18/U_RAMB18>:<RAM
   B16BWER_RAMB16BWER>.  The block is configured to use input parity pin DIBP0.
   There is dangling output for parity pin DOPB0.
WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration
   on
   block:<Inst_system/chipscope_ila_0/chipscope_ila_0/i_chipscope_ila_0/U0/I_NO_
   D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCAD
   E_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[5].u_ramb18/U_RAMB18>:<RAM
   B16BWER_RAMB16BWER>.  The block is configured to use input parity pin DIBP0.
   There is dangling output for parity pin DOPB0.
WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration
   on
   block:<Inst_system/chipscope_ila_0/chipscope_ila_0/i_chipscope_ila_0/U0/I_NO_
   D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCAD
   E_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[0].u_ramb18/U_RAMB18>:<RAM
   B16BWER_RAMB16BWER>.  The block is configured to use input parity pin DIBP0.
   There is dangling output for parity pin DOPB0.
WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration
   on
   block:<Inst_system/chipscope_ila_0/chipscope_ila_0/i_chipscope_ila_0/U0/I_NO_
   D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCAD
   E_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[3].u_ramb18/U_RAMB18>:<RAM
   B16BWER_RAMB16BWER>.  The block is configured to use input parity pin DIBP0.
   There is dangling output for parity pin DOPB0.
WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration
   on
   block:<Inst_system/chipscope_ila_0/chipscope_ila_0/i_chipscope_ila_0/U0/I_NO_
   D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCAD
   E_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[6].u_ramb18/U_RAMB18>:<RAM
   B16BWER_RAMB16BWER>.  The block is configured to use input parity pin DIBP0.
   There is dangling output for parity pin DOPB0.
WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration
   on
   block:<Inst_system/chipscope_ila_0/chipscope_ila_0/i_chipscope_ila_0/U0/I_NO_
   D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCAD
   E_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[1].u_ramb18/U_RAMB18>:<RAM
   B16BWER_RAMB16BWER>.  The block is configured to use input parity pin DIBP0.
   There is dangling output for parity pin DOPB0.
WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration
   on
   block:<Inst_system/chipscope_ila_0/chipscope_ila_0/i_chipscope_ila_0/U0/I_NO_
   D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCAD
   E_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[4].u_ramb18/U_RAMB18>:<RAM
   B16BWER_RAMB16BWER>.  The block is configured to use input parity pin DIBP0.
   There is dangling output for parity pin DOPB0.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
   (RAMB8BWER).  9K Block RAM initialization data, both user defined and
   default, may be incorrect and should not be used.  For more information,
   please reference Xilinx Answer Record 39999.
WARNING:EDK - IPNAME: microblaze, INSTANCE: microblaze_0 - Superseded core for
   architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 31 
WARNING:EDK - IPNAME: lmb_v10, INSTANCE: ilmb - Superseded core for architecture
   'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs
   line 54 
WARNING:EDK - IPNAME: lmb_v10, INSTANCE: dlmb - Superseded core for architecture
   'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs
   line 61 
WARNING:EDK - IPNAME: lmb_bram_if_cntlr, INSTANCE: dlmb_cntlr - Superseded core
   for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 68 
WARNING:EDK - IPNAME: lmb_bram_if_cntlr, INSTANCE: ilmb_cntlr - Superseded core
   for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 77 
WARNING:EDK - IPNAME: mdm, INSTANCE: mdm_0 - Superseded core for architecture
   'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs
   line 174 
WARNING:EDK - IPNAME: proc_sys_reset, INSTANCE: proc_sys_reset_0 - Superseded
   core for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 187 
WARNING:EDK - IPNAME: microblaze, INSTANCE: microblaze_0 - Superseded core for
   architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 31 
WARNING:EDK - IPNAME: lmb_v10, INSTANCE: ilmb - Superseded core for architecture
   'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs
   line 54 
WARNING:EDK - IPNAME: lmb_v10, INSTANCE: dlmb - Superseded core for architecture
   'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs
   line 61 
WARNING:EDK - IPNAME: lmb_bram_if_cntlr, INSTANCE: dlmb_cntlr - Superseded core
   for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 68 
WARNING:EDK - IPNAME: lmb_bram_if_cntlr, INSTANCE: ilmb_cntlr - Superseded core
   for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 77 
WARNING:EDK - IPNAME: mdm, INSTANCE: mdm_0 - Superseded core for architecture
   'spartan6' - M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs
   line 174 
WARNING:EDK - IPNAME: proc_sys_reset, INSTANCE: proc_sys_reset_0 - Superseded
   core for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 187 
WARNING:EDK:4088 - IPNAME: microblaze, INSTANCE: microblaze_0 - Superseded core
   for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 31 
WARNING:EDK:4088 - IPNAME: lmb_v10, INSTANCE: ilmb - Superseded core for
   architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 54 
WARNING:EDK:4088 - IPNAME: lmb_v10, INSTANCE: dlmb - Superseded core for
   architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 61 
WARNING:EDK:4088 - IPNAME: lmb_bram_if_cntlr, INSTANCE: dlmb_cntlr - Superseded
   core for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 68 
WARNING:EDK:4088 - IPNAME: lmb_bram_if_cntlr, INSTANCE: ilmb_cntlr - Superseded
   core for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 77 
WARNING:EDK:4088 - IPNAME: mdm, INSTANCE: mdm_0 - Superseded core for
   architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 174 
WARNING:EDK:4088 - IPNAME: proc_sys_reset, INSTANCE: proc_sys_reset_0 -
   Superseded core for architecture 'spartan6' -
   M:\Night-Sky\Src\RefDesign_14_7_BigBuf\Maxim_FMC_HW\system.mhs line 187 

 

 

 

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Scholar dwisehart
Scholar
15,056 Views
Registered: ‎06-23-2013

Re: Please help me stop beating my head against the wall

I haven't used ChipScope and ISE for a while: now I use Vivado. But it looks like there are several possible problems. This one looks particularly troubling to me:

WARNING:PhysDesignRules:372 - Gated clock. Clock net Inst_system/chipscope_ila_0_icon_control<13> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.

Others can help you more than I can.
Daniel

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Scholar helmutforren
Scholar
15,050 Views
Registered: ‎06-23-2014

Re: Please help me stop beating my head against the wall

Daniel,

 

Thanks.

 

Please note that I really haven't done much of anything to this project.  It was originated as a reference design under version 12.2.  It came to me with a 12.4 install disk.  It worked.  I upgraded it to 14.7.  It continued to work.  Or not?  I really don't remember anymore.  I would have to go back to a saved workspace.

 

NONE of the doc I find addresses using chipscope with SDK.  It all puts chipscope IP outside of SDK, from navigator.  I was thinking about *removing* chipscope cores from the SDK, that were put there by the original ref dsn designer.  Then add them back in from navigator, per doc I can find.  Of course, I hit a snag right away while doing that, long before even considering adding chipscope.

 

So which problem do I fight?  Getting chipscope to work in SDK because I know that design worked in the [distant] past for someone?  Or getting past my new snag in navigator and then adding chipscope there?

 

-Helmut

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Scholar dwisehart
Scholar
15,046 Views
Registered: ‎06-23-2013

Re: Please help me stop beating my head against the wall

If you move forward instead of backwards, at least you know what you created.

You say that the trigger stopped working, but from the warning I pointed out I wonder if ILA is getting a good clock (or trigger) into whatever is icon_control[13].

Daniel
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Scholar helmutforren
Scholar
15,028 Views
Registered: ‎06-23-2014

Re: Please help me stop beating my head against the wall

I'm thinking back to the 1980's.  Yes, I was there.  Microsoft Foundation Classes (MFC).  That was how one coded a GUI program.  MFC was documented as extremely flexible.  However, it was so complicated and therefore so full of pitfalls, actual bugs, and incomplete stubs, that it NEVER worked unless you followed EXACTLY the SINGLE CASE used in the examples for each function.  As a result, it was extremely inflexible.  But you had almost no choice.  So you designed everything you could to fit exclusively the behavior of the examples, almost never using any of the flexibility.  And when you had no choice but to use the flexibility, you made a clone of the involved functions, debugged them, added that necessary new functionality, and from that point forward got locked into that toolkit version.

 

I believe I'm going to have to treat this stuff like that.  I'll go to version 14.7 with a blank slate, rather than an existing, working 12.2 project.  I'll build it up *strictly* in the exact manner of documented examples.  I should be able to get it working.  I won't stray from the sparse examples, which only cover a fraction of the claimed flexibility.

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Explorer
Explorer
14,885 Views
Registered: ‎11-13-2009

Re: Please help me stop beating my head against the wall

Have you had a discussion with your local FAE?  Combing through your warnings and process it seems you could use different approaches to get your answers you need but really an FAE sitting with you for an hour or two would most likely help you resolve the problem.

 

Chipscope (then engine that generating your trigger) is undergoing constant improvements.  So the design being migrated from 12.x to 14.x may have provided a warning about some behavior changes that you were unware to be effecting you given the visibility of the process you choose.

 

One of the posters was spot on about the potential for a clocking problem, but again an FAE could help you figure this out.

 

I wish you luck and sorry this upgrade process didn't go as smoothly as you expected.

TomT...

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