04-02-2013 06:00 AM
I am running in a problem with Xilinx Power Analyzer. I am currently using the command line version of the tool called "xpwr".
My flow is:
- Synthesizing, Mapping and Placing and Routing the design
- Generating a simulation file using the tool "netgen" (verilog output)
- SImulating the time_sim.v file using ModelSim (now named QuestaSim) and dumping the signal acitivities in a vcd-file
- Calling "xpwr" and giving the value change dump (vcd), constraints (pcf) and placed and route design (ncd) as parameters
The result is a power-report in which all confidences are set to "HIGH" but at the end of the report I get some errors for input/output-signals which look like this:
ERROR:Power:1653 - Duty cycle <195.00> must be in range [0..100]% for IN2<4>.
Interestingly those errors are presented for those input/output-signals which have a "signal rate" of exactly 0.06 in the IO-table (which I can see when I call xpwr with the "-v" option) of the power-report.
My question is:
1. Can I do anything to resolve this problem or is there an xpwr-bug which produces this kind of error-message?
2. What exactly is the information which is provided by this error message.
Thank you for additional information.
04-03-2013 03:56 AM
I just want to give some additional information.
In my opinion this error message of XPower seems to be a bug, but I am not sure about it.
I have the following understanding of the Xilinx-Terms:
- signal rate: average switching frequency of a signal
- %high: Ratio of the signal being in the "1"-state
- duty cycle: according to the xilinx glossary, this term is equivalent to %high
Whenever I create a design and one of the inputs or one of the outputs is permanently set to "1", this signal leads to the error message:
ERROR:Power:1653 - Duty cycle <200.00> must be in range [0..100]% for SIGNALNAME.
A duty cycle of 200 is impossible, if duty cycle means the percentage of the time the signal is set to "1". In the table which xpwr produces those signals are correctly stated as "signal rate=0", "%High=1".
So: Is this a bug in xpwr/xpa or am I wrong in my conclusion?
11-17-2014 12:49 AM
Try generating SAIF file using Isim and using it in Xpower Analyzer instead of VCD file. You may not get this error any more.