06-20-2014 06:39 AM
We have developed a model (for QR decomposition) in System Generator and generated the HDL code using HDL netlist generation with test bench. As a next step, we have opened the generated project in ISE. We have generated a "post place and route simulation model". Then using ISIM simulator, we have verified the functionality of the developed block (which came out to be the same as that obtained from system generator).
Next we wanted to verify the same signals using ChipScope. There are 10 signals to be verified each of 16 bit width. Out of these, 4 signals are coming properly as desired. Rest of the signals are not obtained.
Can anyone help us to find why we are not able to see the results properly in chipscope but only in post par simulation and from system generator.
Please do reply at the earliest.
06-20-2014 07:01 AM
We have one more doubt..
Can we connect the system clock (Virtex 6 board) to the trigger port of the chipscope.
Also, the trigger condition has been set to "R"
But, once we trigger the signal, it is showing that "Waiting for trigger. Sample buffer has 0 samples"
What would be the problem??
06-20-2014 07:46 AM
What is your clock source for Chipscope? Also the system clock? No, you cannot use the same clock for both. Generally you cannot sample clocks with Chipscope because everything Chipscope samples should be in the same clock domain or there will be setup and hold problems.
If you just want to manually trigger a sample without a trigger source, you can do that. You can even take any signal and make its trigger condition to be X, which does the same thing and allows automatically repeated captures.
More information is needed on what you are trying to instrument to help further.
06-20-2014 08:00 AM
We have to see results which are obtained after each clock cycle i.e, say we have 2 signals S1 and S2.
After a valid value from S1, in the next clock cycle a valid S2 value should be obtained.
Initially we were connecting the signals to be viewed to the trigger ports and verifying.
In that case, we were seeing the results at random locations(random time instances).
So, to see the outputs in a sequential order we have connected the signals to the data port of ILA and connected the trigger port to the system clock (which is same as the signal connected to the clock port of the chipscope). And we have set the condition in Trigger Setup to "R".
Then, we are not able to sample the data.
06-20-2014 08:11 AM
When you trigger off of S1, you should be able to capture S2 for at least the next 1,024 clock cycles. If you need to trigger off of S1 followed by S2 you can do that with an advanced trigger.
Trying to trigger off of the clock will give you nothing because when you sample the clock it is always the same level if it is the same clock.
06-20-2014 09:09 AM
If you put the clock out of phase and sample it, it will always sample high or always sample low, depending on how much you put it out of phase. You might as well trigger off of Vcc or Gnd if that is the trigger you are going to use.
Explain again your problem. S1 triggers Chipscope and you collect 1,024 samples of S2. You also want to do what, that this does not do?
06-20-2014 09:25 AM
06-20-2014 09:36 AM
The trigger and all inputs are sampled synchronously by the probe clock.
Are S1 and S2 from registers driven by the same clock? If not, you have a problem: you cannot suddenly switch clocks in the middle of a measurement.
Did Chipscope create two probes for you with different source clocks for S1 and S2? If so you are going to have to reclock one of the signals into the other signal's clock domain.