02-24-2017 07:52 AM
I am trying to run the "Virtex-7 VC7203 IBERT Getting Started Guide (UG847)", as I'll need to use the GTX transceivers in a future project. I am using Vivado 2015.1 and the version 2015.1 of the UG847. I am following the UG step by step. The only difference is that I am using Q113 instead of Q115. Consequently, I had to set the SYSACE-2 CFG switch (SW8) accordingly: ADR2, ADR1 and ADR0 equal to ON. After setting up Vivado, programming the board (using the .bit and .ltx files for Q113 obtained from Xilinx webpage), starting the SuperClock-2 Module (setup_scm2_156_25.tcl script) and creating the Serial I/O Links, the status of "COMMON_X1Y0" PLL appears as "Not Locked" and the status of the MGTs is "No Link". This way, I am not able to view the GTX Transceiver operation.
I even tried some of the suggestions shown in the UG to overcome this situation (increase TX differential swing, TX reset and BERT reset), but none of them work. I also checked the output of the TCL console (attachment: "tcl_console_msgs.txt"), but i didn't notice any anomaly.
I am new to this board and have no previous experience in working with GTX transceivers. Any help, comments or hints would be valuable.
Thanks for your attention!
03-10-2017 10:54 AM