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11,925 Views
Registered: ‎07-26-2013

Programming fail with JTAG

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Hi,

  The purpose of this post to understand the relationship of JTAG prgramming with different power rails of the FPGA.

  We are having some problem programming the FPGA through the JTAG ..... sometimes.

 

Let me explain the setup.

 

Our FPGA interfaces to a dummy substrate of SOC.The dummy substrate does nothing but connects the FPGA side IO ports of substrate to varius peripherals on the board like SPI Flash, UART (through level shifters), I2C etc.

Whenever the substrate is placed in the socket, sometimes the JTAG programming fails.

Our suspicion is that whenever the substrate is populated, some of the IO pins of FPGA that are connected to various peripherals through the substrate get shorted (due to rreasons unknown) and FPGA might be consuming lot of current and jtag programming fails.

 

Whenever we remove the substrate from socket, the FPGA contact with peripherals is broken, and the JTAG programming succeeds every single time with the same bitstream.

 

However,same bitstream when loaded from BPI flash loads nicely and DONE pin is high consistently regardless of the substrate present or absent.

 

So this makes me wonder what is it that JTAG programing does differently as compared to same bitstream loaded from FPGA?

 

Why doesnt the FPGA lose its configuration when loaded from BPI, while JTAG programming fails for same bit file?

 

We have been struggling for past 2 weeks to figure out whether its IO ports of FPGA connecting to varios peripherals are causing a problem or what.

 

One additional note: All Bitstream are built with the bitgen option to tristate unused/undriven ports of FPGA.

FPGA is V7330T1157-2 and impact 14.2 is used for programming.bitstream generated using Vivado

 

Any hint or piece of suggestion is most welcome.

 

Thanks

-Sachin

 

 

 

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20,071 Views
Registered: ‎07-26-2013

Hi,

 Finaly i found the problem. The issue was with the PUDC_B pin connection. This pin was connected to ground.

Due to this all the IO pins were pulled up DURING configuration.This was causing some issues as JTAG config takes longer to configure compared to loading from BPI flash.

 

We still do not know what peripherals or power supplies were getting impacted.But it showed failure sometimes. Many times JTAG would work, so looks like something would get accumulated over a period of time and then fail suddenly.

 

Anyways by connecting PUDC_B high on board, all the IOs were Trisated during configuration and FPGA programming passes all the time.

 

Infact i would say in the user guide, a recommended setting (of tristating IOs) for PUDC_B would be really be helpful.

Request Xilinx to recommend users to connect this pin to 1, so that such unknown accidents dont happen on board.

 

Thanks,

Sachin

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Community Manager
Community Manager
11,899 Views
Registered: ‎07-23-2012
Hi Sachin,

Please answer the following queries-

1. When you say that JTAG configuration fails, what is the error do you see? Read the status register to get a clue on this. Refer to http://www.xilinx.com/support/answers/34909.htm

2. Are you able to detect the FPGA by initializing the JTAG chain with substrate on?

3. Can you probe the power supply rails of fpga when substrate is connected and see if you see any irregularities?

Regards,
Krishna
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Highlighted
20,072 Views
Registered: ‎07-26-2013

Hi,

 Finaly i found the problem. The issue was with the PUDC_B pin connection. This pin was connected to ground.

Due to this all the IO pins were pulled up DURING configuration.This was causing some issues as JTAG config takes longer to configure compared to loading from BPI flash.

 

We still do not know what peripherals or power supplies were getting impacted.But it showed failure sometimes. Many times JTAG would work, so looks like something would get accumulated over a period of time and then fail suddenly.

 

Anyways by connecting PUDC_B high on board, all the IOs were Trisated during configuration and FPGA programming passes all the time.

 

Infact i would say in the user guide, a recommended setting (of tristating IOs) for PUDC_B would be really be helpful.

Request Xilinx to recommend users to connect this pin to 1, so that such unknown accidents dont happen on board.

 

Thanks,

Sachin

View solution in original post

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