04-30-2019 12:26 PM - edited 04-30-2019 12:28 PM
When I add signals to debug using Chipscope I see that a 300 MHz clock is appended to my XDC file.
The line looks as follows:
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
I have some questions about this clock:
1. What exacly is it used for ?
2. I see that this clock's frequency can be changed using "cell properties" in the debug menu (attached picture). How is it generated?
3. Can I gain access to this clock and use it as any other user clock ?
04-30-2019 01:15 PM
Hi @shaikon ,
This is the clock for the debug hub, which is a piece of IP that connects all the debug cores (such as ILA, IBERT, VIO, etc) that might exist in a design and process their communcation to the JTAG interface.
Since you added an ILA to your design, the debug hub was automatically added as well.
You should not modify this clock frquency (unless you're having issues with your debug cores and need to modify it) and you can not tap it and use this clock for something else in your design.
If you need a 300MHz clock for your logic, you can use the Clocking Wizard IP and synthesize one.
04-30-2019 02:03 PM
And I assume that for every ILA in my design Vivado will implement a clock domain crossing circuit from that ILA's domain to the Debug Hub's domain ?
If so - is there a good reason why the Debug Hub's clock is set to be so high by default ?
What would be the negative effects of slowing it down ?
05-03-2019 01:25 PM
No, the dbg_hub is just one for the whole device, and there's no clock feeding from the dbg_hub to the ILA.
The ILA get's it's own clock, which is local and normally the same clock being used in the logic where the ILA is probing.
What are the issues you are concerned about? Are you seeing any issues with this implementation?
05-04-2019 02:30 AM - edited 05-04-2019 02:30 AM
"No, the dbg_hub is just one for the whole device, and there's no clock feeding from the dbg_hub to the ILA."
I think you missread my response - I never said that there're many dbg_hub clocks...this is what I wrote:
I assume that for every ILA in my design Vivado will implement a clock domain crossing circuit from that ILA's domain to the Debug Hub's domain
"What are the issues you are concerned about? Are you seeing any issues with this implementation?"
I'm thinking whether it possible to relax the tool's timing efforts by lowering the original 300MHz frequency. This is why I asked "what would be the negative effects of doing so?"