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chenxuol
Contributor
Contributor
4,621 Views
Registered: ‎07-18-2014

Question about IBERT sysyem clock frequency setting for GTP in Virtex5

hello,I am using IBERT to test the GTP in Virtex5 board with ISE 12.4.I have GTP tile clock only ,and the frequency is 212.5MHz.but the IBERT for Virtex5 GTP seems to support 10~100MHz only.

How can I test the Virtex GTP with 212.5MHz GTP tile clock?

ibert-12.4-warning.jpg
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3 Replies
vijayak
Xilinx Employee
Xilinx Employee
4,579 Views
Registered: ‎10-24-2013

Hi @chenxuol

I have not tested this but the following approach may help.

Generate the IBERT design with the system clock set to the internal system clock frequency that will be used in the core (10MHz to 100MHz).  
In the generated top file, instantiate a PLL or DCM between the input clock IBUFGDS and the BUFG that drives dclk into the IBERT design.
You may also need change the ucf constraints accordingly.

Thanks,Vijay
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chenxuol
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Registered: ‎07-18-2014

I tried to use the 212.5MHz GTP tile clock as the IBERT system clock with instantiating a PLL,but I faild.

The board I want to test has two kinds of GTP tile clock,one bank using 100MHz, and the other banks using 212.5MHz.There isn't any local system clock on the board.I just want to test the banks with 212.5MHz.

The IBERT system clock range is 10MHz~100MHz.If can I use the 100MHz GTP tile clock as the system clock?Would someone please show me step by step how it can be worked?

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chenxuol
Contributor
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Registered: ‎07-18-2014

I want to rebuild the IBERT project manually,referring to the AR#31684 and AR#31685

https://www.xilinx.com/support/answers/31684.html

https://www.xilinx.com/support/answers/31685.html

https://forums.xilinx.com/t5/Virtex-Family-FPGAs/How-Can-I-Set-A-PIN-to-High-or-Low-in-UCF/m-p/75921#M6603

 

question one:The ibert_v5gtp_powerup.xz in 31684_1.zip cannot be decompressed,does that matter?

 

question two:when I run the bat file,I cannot generate the ngd file,the error log is shown as below:

 

Checking expanded design ...
WARNING:NgdBuild:486 - Attribute "SIM_DEVICE" is not allowed on symbol
"pll_refclk" of type "PLL_ADV". This attribute will be ignored.
ERROR:NgdBuild:604 - logical block 'U_ICON' with type 'icon_2_port' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
case mismatch between the block name and the edif or ngc file name, or the
misspelling of a type name. Symbol 'icon_2_port' is not supported in target
'virtex5'.
ERROR:NgdBuild:604 - logical block 'iUseVioEq2.U_VIO' with type 'vio_ibertgtp'
could not be resolved. A pin name misspelling can cause this, a missing edif
or ngc file, case mismatch between the block name and the edif or ngc file
name, or the misspelling of a type name. Symbol 'vio_ibertgtp' is not
supported in target 'virtex5'.
ERROR:NgdBuild:455 - logical net 'control0<3>' has multiple driver(s):
pin control0<3> on block U_ICON with type icon_2_port,
pin O on block U_DRP_WRAP/U_DRP_ICON/control0_out623 with type MUXF7

 

What should I do to solve the problem?

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