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Registered: ‎05-18-2018

Question about net/slice naming in Vivado/ILA

I am placing debug probes on a 4-bit bus in my synthesized design in Vivado 2019.1.

Based on my netlist in the Synthesis flow and my Capture Setup panel in ILA, I have selected the followng nets for observation (see picture):

  • top_i/lcd/Flex_LCD_Controller_0/U0/ultra_ali3_controller_core_l/videoout/gearbox_28to4/txc_piso/tx_data_reg_n_0_[0:0]
  • top_i/lcd/Flex_LCD_Controller_0/U0/ultra_ali3_controller_core_l/videoout/gearbox_28to4/txc_piso/tx_data_reg_n_0_[1:1]
  • top_i/lcd/Flex_LCD_Controller_0/U0/ultra_ali3_controller_core_l/videoout/gearbox_28to4/txc_piso/tx_data_reg_n_0_[2:2]
  • top_i/lcd/Flex_LCD_Controller_0/U0/ultra_ali3_controller_core_l/videoout/gearbox_28to4/txc_piso/tx_data_reg_n_0_[3:3]

However, in ILA, when I add these nets from the Capture Setup to the Waveform window, they ALL show up as

  • tx_data_reg_n_0_[3:3]
  • tx_data_reg_n_0_[3:3]
  • tx_data_reg_n_0_[3:3]
  • tx_data_reg_n_0_[3:3]

and the waveforms are identical; it does look like the bit 3 is the only one being displayed, and Vivado is, for some reason, ignoring bits 0, 1, 2.


can only add but 3_3.png


Am I misunderstanding their net naming? How can I view bits 0-2?



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