02-04-2020 08:20 AM
concerning the clock frequency of the clock buffer feeding the ILA, I simulated the "example_top" design and checked the MIG-generated clock frequency: it stands at 200MHz, which is equal to the system input clock frequency.
Currently, the differential clock signal is entering into an IBUFDS and successively into a BUFG for feeding the ILA with a free running clock. Processes are also updated on this clock. Therefore, logically, no difference stands between the two designs. In fact, simulation provide an equivalent test result.
Nevertheless, probed signals when opened in the Vivado Hardware Manager in the ILA are kept at a zero constant value despite the equal clock frequency. How should I proceed?
Thanks in advance. Best regards.
02-05-2020 05:24 AM
sorry for multiple posting. Just to keep you updated, the issue was concerning the management of the reset signal. Nevertheless, now if triggering the ILA, the following error message appears in the HW manager:
ERROR: [Labtools 27-3312] Data read from hw_ila [hw_ila_1] is corrupted. Unable to upload waveform.
I keep digging. If any suggestion arises, please reply.
Thanks in advance.