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dtonn
Visitor
Visitor
14,106 Views
Registered: ‎05-22-2014

Re: Which clock does dbg_hub clock XSDB_CLK_I connect to?

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Is there any way to control which ILA is connected to ila_0?
I have 3 ILAs, and it's picking the least desirable ILA to choose as ila_0, and hence the source of the dbg_hub clock.
The clock for this ILA comes from a BUFR, and it appears that the clock used by dbg_hub connects out of dbg_hub to every BRAM in every ILA, and therefore must be driven by a BUFG.
If Vivado had chosen either of my other two ILAs it would have been fine.
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vemulad
Xilinx Employee
Xilinx Employee
23,044 Views
Registered: ‎09-20-2012

Hi,

 

Execute below commands to choose your own stable clock that needs to be connected to dbg_hub

 

disconnect_debug_port dbg_hub/clk

connect_debug_port dbg_hub/clk [get_nets <net name of the clk signal of interest>]

 


Thanks,

Deepika.

Thanks,
Deepika.
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debrajr
Moderator
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Registered: ‎04-17-2011
Moving to Design Tools - Others as this board is for Simulation queries.
Regards,
Debraj
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vemulad
Xilinx Employee
Xilinx Employee
23,045 Views
Registered: ‎09-20-2012

Hi,

 

Execute below commands to choose your own stable clock that needs to be connected to dbg_hub

 

disconnect_debug_port dbg_hub/clk

connect_debug_port dbg_hub/clk [get_nets <net name of the clk signal of interest>]

 


Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

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vemulad
Xilinx Employee
Xilinx Employee
14,036 Views
Registered: ‎09-20-2012

Hi @dtonn 

 

Is this issue resolved?

 

Thanks,

Deepika.

Thanks,
Deepika.
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dtonn
Visitor
Visitor
14,029 Views
Registered: ‎05-22-2014
"connect_debug_port dbg_hub/clk" solved my problem.
Thank you. I would not have figured that out no matter how many Users Guides I read.
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krynn1978
Visitor
Visitor
7,649 Views
Registered: ‎05-15-2015

Hi @vemulad

 

I have the very same problem as dtonn (using Vivado 2016.2). Unfortunately in my case the connect_debug_port constraint does not produce any effect (Vivado keeps on selecting another clock for the dbg_hub).

The syntax seems to be correct (if i execute the command in tcl shell it does not produce any error), I have no warnings or errors relating to that constraint.

 

Any suggestion?

Thanks

 

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mamisadegh3
Explorer
Explorer
7,375 Views
Registered: ‎09-19-2010

The above provided solution is not really useful.

You can not use disconnect_debug_port inside the xdc.

 

Now vivado, insists on using a wrong clock for the dbg_hub,

with the above solution, after every synthesis you have to disconnect that clock and connect your desired correct clock to the core.

Which is not possible in practice.

 

So, the issue is still there.

I do not understand why vivado does not look at the

 

connect_debug_port dbg_hub/clk [get_nets desired_clk_net]

 

command inside the constraints file. It just connects the clk port of dbg_hub to wherever he likes! which is totally incorrect!

 

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mamisadegh3
Explorer
Explorer
7,357 Views
Registered: ‎09-19-2010

Hi,

 

I did further investigations, and as of vivado 2016.3

even the proposed solution in the above is incorrect.

 

Even if you disconnect the dbg_hub clk net, and issue the command to connect it to another net,

 

still Vivado goes ahead in the synthesis with its own selected net. It does not listen to you at all.

 

The very interesting point is that Vivado does not even look at the properties of the clock net he chooses for dbg_hub.

If you have a 2.5MHz clock, although you have indicated in your xdc this is a 2.5MHz net, Vivado just uses that net for the clock input of dbg_hub, which is incorrect because dbg_hub will not work with clock frequencies under 25MHz.

 

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patcher33
Participant
Participant
2,386 Views
Registered: ‎02-01-2018

Hi,

 

have the same problem with vivado 2018.2.2.

The solution with the "disconnect... " and "connect_debug_port dbg_hub/clk" doesn't help

The connect_debug_port  statement in the xdc is ignored.

 

Is it an old bug? How Vivado decides which clock to use for the hub?

 

regards

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leoleonis
Observer
Observer
475 Views
Registered: ‎07-15-2019

ok, this is very old, but I didn't find anything newer. 

indeed it's very annoying that there is no way to choose the debug hub clock in the setup debug wizzard. 

usually I have more than one clock domain, and therefore more ila-cores. but not all of the clocks are free running - and again and again vivado selects a clock for the debug hub, which is not free running.

is there another solution for this?

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