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roberthale88
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Registered: ‎08-23-2012

Readback of SRLs on Kintex Ultrascale

I'm attempting to run readback (readback_hw_device) on a Kintex Ultrascale programmed with a very simple counter design. A bit of the counter is fed into an SRL (the provided "SRL16E"). Perhaps this is a lack of understanding about SRLs or LUTs, but the 64 bits I readback that represent the SRL are the same regardless of what value the SRL should have been seeing before stopping the clock and performing readback. That value is:

 

0000000000000000000000000000000100000000000000000000000000000001

 

Can anyone explain this to me? I want to be able to see what 16 values are currently passing through the shift register (SRL). Since I'm tying it to the first bit of the counter, in theory it should be alternating 1s and 0s (though I have tried other bits of the counter; nothing changes readback from producing the above value). Other readback values from FFs are accurate and as expected.

 

I've already read through this XAPP that explains how an SRL works to a degree, but I wasn't able to figure it out from that.

 

Thank you for any help.

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austin
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Registered: ‎02-27-2008

r,

 

SRL are dynamic, so they are not read back (they appear as a fixed pattern).

 

The 64 bit LUT can be a 32 bit shift register (it uses the bits in a master-slave when in SRL mode).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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roberthale88
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Registered: ‎08-23-2012

Austin,

 

Thanks for your reply. To confirm, this means the values being shifted through an SRL cannot be seen using readback? Do any methods exist to see these values, except waiting for them to shift to the Q output?

 

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austin
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Registered: ‎02-27-2008

r,

 

Correct.

Austin Lesea
Principal Engineer
Xilinx San Jose
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roberthale88
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Registered: ‎08-23-2012

That's good to know. XAPP1230 certainly implies that readback can reveal the contents of an SRL:

 

"Readback capture provides the ability to read the current user state of internal CLB registers, block RAM, distributed RAM, and SRL contents to check for proper design functionality."

 

I've submitted feedback about the XAPP through Xilinx's Website Feedback page.

 

Thanks again!

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austin
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Registered: ‎02-27-2008

r,

 

A trick is to set the SRL/LUTRAM bits to 'OFF' so that the readback could the see what is there.  When configured for LUTRAM/SRL, readback is masked so that dynamic memory changes do not appear as upset bits.  But, you can change that by asserting the bits back to LUT mode.

Austin Lesea
Principal Engineer
Xilinx San Jose
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roberthale88
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Registered: ‎08-23-2012

How do I access SRL/LUTRAM bits to turn them off?

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austin
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Registered: ‎02-27-2008

It is called 'bitstream hacking,'

 

And, you are on your own for that.

 

Typically, a design is compared at the .bit level that differs by just one attribute (like LUTRAM to LUT).  A diff of the bitstream reveals the bit being set.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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roberthale88
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Registered: ‎08-23-2012

Ah, understood.

 

Thanks for your help.

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