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2,491 Views
Registered: ‎01-08-2013

Setup debug clock issue

Hi Everyone,

I'm debugging a design using Vivado2015.

When I do setup debug after synthesis, I got a dialog as following figure shows where the clock domain for some signals are wierd.The "u_ddr_sub_top/u_ddr_sub_top_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep_26_0" actually is not a clock.set_debug01.png

 

I try to change the clock domain by right click my mouse and use "select clock domain" menu, the clock domain for these signals mentioned above should be "u_ddr_sub_top/u_ddr_sub_top_mig/u_ddr3_infrastructure/clk_pll_i", however this clock is not in the listed dialog as figure below shows.

set_debug02.png

 But the clock domain "u_ddr_sub_top/u_ddr_sub_top_mig/u_ddr3_infrastructure/clk_pll_i" do exist in my design and after implementation it can be reported in "report clock network".

What's wrong with my operation and how can I fix this problem?

 

Any hints and suggestions are appreatiated.

Thanks!

Simon 

 

 

set_debug01.png
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2 Replies
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Xilinx Employee
Xilinx Employee
2,483 Views
Registered: ‎04-16-2012

Hi @simon_mviewtech

 

Open the Synthesized design and run report clock networks and look for the clock: u_ddr_sub_top/u_ddr_sub_top_mig/u_ddr3_infrastructure/clk_pll_i

 

Thanks,

Vinay

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2,444 Views
Registered: ‎01-08-2013

Hi Vinay,

Thanks for your reply. The synthesied result doesn't contain the clock u_ddr_sub_top/u_ddr_sub_top_mig/u_ddr3_infrastructure/clk_pll_i when I do reort clock networks operation.

However, when I do report timing summary, it exists in Intra-clock paths as clock sources.

Thanks!

Simon

 

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