05-23-2017 08:07 PM
I'm debugging a design using Vivado2015.
When I do setup debug after synthesis, I got a dialog as following figure shows where the clock domain for some signals are wierd.The "u_ddr_sub_top/u_ddr_sub_top_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep_26_0" actually is not a clock.
I try to change the clock domain by right click my mouse and use "select clock domain" menu, the clock domain for these signals mentioned above should be "u_ddr_sub_top/u_ddr_sub_top_mig/u_ddr3_infrastructure/clk_pll_i", however this clock is not in the listed dialog as figure below shows.
But the clock domain "u_ddr_sub_top/u_ddr_sub_top_mig/u_ddr3_infrastructure/clk_pll_i" do exist in my design and after implementation it can be reported in "report clock network".
What's wrong with my operation and how can I fix this problem?
Any hints and suggestions are appreatiated.
05-23-2017 08:27 PM
Open the Synthesized design and run report clock networks and look for the clock: u_ddr_sub_top/u_ddr_sub_top_mig/u_ddr3_infrastructure/clk_pll_i
05-24-2017 04:27 AM
Thanks for your reply. The synthesied result doesn't contain the clock u_ddr_sub_top/u_ddr_sub_top_mig/u_ddr3_infrastructure/clk_pll_i when I do reort clock networks operation.
However, when I do report timing summary, it exists in Intra-clock paths as clock sources.