05-29-2014 07:57 PM
I generated ICON and ILA using coregen and added them to my design. I then implemented the design to FPGA and the final output looked good.
But some of the signals in the chipscope didn't seem to work correctly (equal to zero all the time). It shouldn't be like this because the final output depend on these signals. If these signals were equal to zeros, then the output would be zero also.
I wonder if this is due to the signals trimming (or maybe being merged)? I know there are common question about missing signals when someone use core inserter. Is it same to my case also?
05-29-2014 08:17 PM - edited 05-29-2014 10:52 PM
This may be a trimming scenario, to confirm check the synthesis report for details of trimming of signals.
The best possible way to check the trimming or optimization is by checking the connectivity through synthesized netlist.
Can you verify this?
Do you have a chance to check post-synthesis simulation to confirm the logic/functional correctness?
05-29-2014 10:48 PM
I didn't check the post-synthesis simulation but I did check it in modelsim simulation.
Is there a way to avoid that? I tried several ways suggested in other threads, e.g. (* KEEP = "TRUE" *). But it doesn't work.
Any other suggestions would be greatly appreciated.
05-29-2014 11:35 PM
I would first suggest to look for the signal connectivity in synthesized netlist and see if is connected as expected.
This will give us the clue of whether to have the KEEP or any attribute to preserve the optimization.
Can you please share the schematic snapshot of the signal?
06-03-2014 03:15 AM
The name of the signal is 'hbf_out_vld[15:0]'. But I guess it has been trimmed and merged with 'tar_out_vld' (which are identical).
I tried to add 'tar_out_vld' to chipscope but it still remain at zero.
Please find attachment of the schematic.
06-06-2014 12:08 AM