UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor yulek
Visitor
11,471 Views
Registered: ‎05-21-2014

Signals in Chipscope.

I generated ICON and ILA using coregen and added them to my design. I then implemented the design to FPGA and the final output looked good.

 

But some of the signals in the chipscope didn't seem to work correctly (equal to zero all the time). It shouldn't be like this because the final output depend on these signals. If these signals were equal to zeros, then the output would be zero also.

 

I wonder if this is due to the signals trimming (or maybe being merged)? I know there are common question about missing signals when someone use core inserter. Is it same to my case also?

 

Thanks.

0 Kudos
6 Replies
Xilinx Employee
Xilinx Employee
11,468 Views
Registered: ‎07-01-2010

Re: Signals in Chipscope.

Hi,

 

This may be a trimming scenario, to confirm check the synthesis report for details of trimming of signals.

 

The best possible way to check the trimming or optimization  is by checking the connectivity through synthesized netlist.

 

Can you verify this?

 

Do you have a chance to check post-synthesis simulation to confirm the logic/functional correctness?

 

 

Regards,

Achutha

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------
0 Kudos
Visitor yulek
Visitor
11,457 Views
Registered: ‎05-21-2014

Re: Signals in Chipscope.

I didn't check the post-synthesis simulation but I did check it in modelsim simulation.

 

Is there a way to avoid that? I tried several ways suggested in other threads, e.g. (* KEEP = "TRUE" *). But it doesn't work.

 

Any other suggestions would be greatly appreciated.

 

Cheers.

0 Kudos
Xilinx Employee
Xilinx Employee
11,451 Views
Registered: ‎07-01-2010

Re: Signals in Chipscope.

Hi,

 

I would first suggest to look for the signal connectivity in synthesized netlist and see if is connected as expected.

This will give us the clue of whether to have the KEEP or any attribute to preserve the optimization.

 

Can you please share the schematic snapshot of the signal?

 

Regards,

Achutha

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------
0 Kudos
Visitor yulek
Visitor
11,409 Views
Registered: ‎05-21-2014

Re: Signals in Chipscope.

The name of the signal is 'hbf_out_vld[15:0]'. But I guess it has been trimmed and merged with 'tar_out_vld' (which are identical). 

 

I tried to add 'tar_out_vld' to chipscope but it still remain at zero. 

 

Please find attachment of the schematic.

xilinx_forum.jpg
0 Kudos
Visitor yulek
Visitor
11,383 Views
Registered: ‎05-21-2014

Re: Signals in Chipscope.

I tried this:

 

http://www.xilinx.com/support/answers/44464.html

 

But it still doesn't seem to work. Any other suggestion?

 

0 Kudos
Xilinx Employee
Xilinx Employee
11,363 Views
Registered: ‎07-01-2010

Re: Signals in Chipscope.

Hi ,

Can you please try using the keep_hierarchy yes option to preserve the hierarchy?

This will preserve the hierarchy and optimization across boundaries is not done.

If this doesn't help please share the design so that i can check the details and provide you the solution.

Regards,
Achutha
---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------
0 Kudos