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greenleafone7
Observer
Observer
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Registered: ‎10-23-2020

Simulation not starting

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I have built my project, added my verilog and mem files, selected Basys3 as my board. I can Synthesize and Implement it. My problem is when trying Behavioural Simulation. Nothing seems to be happening if I press 'Run All', while if I run for a specific time duration then my simulation will instantly move X amount of time with no changes on the variables.

 

I don't know how to tackle this exactly but during the 'Run Implementation' step I get a message that one timing constraint was not satisfied.

greenleafone7_0-1603491704470.png

 

As well as a number of warnings, that make me suspect my constraints file

greenleafone7_1-1603491859543.png

 

Can someone explain to me what I am doing wrong?

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drjohnsmith
Teacher
Teacher
904 Views
Registered: ‎07-09-2009

I think you need to take step back, and look at what simulation does.

Simulation works on you raw code,
whilst synthesis takes your code, and complies it to fit in the fpga,

as such, you normally simulate and debug before you synthesise.

simulation, as it does not go into a fpga, can represent things such as unknown logic levels, and tri state, which do not exist in the fpga.

so if you do code such as A <= not(A) , unless you have initialised A, that will show as a constant unknown, as not( unknown) is unknown. This is good as it helps you identify which code you need to initialise and which you don't which makes a more efficient FPGA .

A simulation also needs something to drive the inputs to the code your simulating, note you do not have to , and indeed most the time you will not be simulating the complete design, you simulate sub parts individualy.

The reason is called test coverage.

A VERY simple example , over used as an example. but.
assume a simple 2 input gate, that need 4 test "vectors" to test all combinations,
If you now had three of these gates cascaded, you have 4 inputs, 16 test vectors needed to test every combination. But if you have already tested the 2 input gate 100%, then you only need to test the routing between the gates in the top level design, thats 4 vectors for a gate, and two more for the design, 6 vectors.

OK, not much difference, but multiply that up to designs that have millions of gates, its impossible to test every combination at the top level, in fact its never in real life possible to test even the smaller units 100% , but ti gives you much more coverage.

Looking at your error messages,
it looks like you design has problems with bits joined.

These will show up very easily in a test bench simulation, you will spend most of your time in simulation over time, very little in synthesis, so its well worth while learning simulation at the very beginning.

At the very first level,

  you need to decide which files to add to the simulation set,

     an XDC file, being timing and pin placement , has no need to be simulated

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

7 Replies
drjohnsmith
Teacher
Teacher
905 Views
Registered: ‎07-09-2009

I think you need to take step back, and look at what simulation does.

Simulation works on you raw code,
whilst synthesis takes your code, and complies it to fit in the fpga,

as such, you normally simulate and debug before you synthesise.

simulation, as it does not go into a fpga, can represent things such as unknown logic levels, and tri state, which do not exist in the fpga.

so if you do code such as A <= not(A) , unless you have initialised A, that will show as a constant unknown, as not( unknown) is unknown. This is good as it helps you identify which code you need to initialise and which you don't which makes a more efficient FPGA .

A simulation also needs something to drive the inputs to the code your simulating, note you do not have to , and indeed most the time you will not be simulating the complete design, you simulate sub parts individualy.

The reason is called test coverage.

A VERY simple example , over used as an example. but.
assume a simple 2 input gate, that need 4 test "vectors" to test all combinations,
If you now had three of these gates cascaded, you have 4 inputs, 16 test vectors needed to test every combination. But if you have already tested the 2 input gate 100%, then you only need to test the routing between the gates in the top level design, thats 4 vectors for a gate, and two more for the design, 6 vectors.

OK, not much difference, but multiply that up to designs that have millions of gates, its impossible to test every combination at the top level, in fact its never in real life possible to test even the smaller units 100% , but ti gives you much more coverage.

Looking at your error messages,
it looks like you design has problems with bits joined.

These will show up very easily in a test bench simulation, you will spend most of your time in simulation over time, very little in synthesis, so its well worth while learning simulation at the very beginning.

At the very first level,

  you need to decide which files to add to the simulation set,

     an XDC file, being timing and pin placement , has no need to be simulated

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

greenleafone7
Observer
Observer
855 Views
Registered: ‎10-23-2020

Makes sense. I knew what the constraints files are for, wasn't sure if I need to run synthesize before simulating or not though. Nonetheless I am trying to run an open source project that runs fine on other computers. Why is the simulation stopping immediately after me pressing the button though, or just directly moves to the specified time if I use Shift + F2 without any effect?

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drjohnsmith
Teacher
Teacher
799 Views
Registered: ‎07-09-2009
Do you have other examples that do work on the computer that has this feature ?
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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greenleafone7
Observer
Observer
750 Views
Registered: ‎10-23-2020

So if I change something on my .v files, I need to run simulation again. If I change something on my .mem file then I need to reload the simulation?
I think I am getting the basics now. Thanks.

bruce_karaffa
Scholar
Scholar
742 Views
Registered: ‎06-21-2017

Just checking.  You do have a test bench that generates clock(s) a reset and any other signals that your unit under test needs and also instantiates the unit under test?

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greenleafone7
Observer
Observer
733 Views
Registered: ‎10-23-2020

Yes. Now I do. I was missing the whole idea behind creating proper tests and having the correct file set up as `top`.

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drjohnsmith
Teacher
Teacher
719 Views
Registered: ‎07-09-2009
Well done you for working it out and even more well done you for getting back to the forum
Give if luck.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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