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Registered: ‎03-20-2018

System ILA signal names incorrect

I'm having a problem where the interface names on the System ILA are correct, but the individual signal names are often wrong. 

The design I'm working on has several pieces of custom IP, named RRA, VFP, and VT. Each has an AXI-Stream Slave and Master Interface. The master interface of each block is connected to an AXIS interconnect's slave input, and the master output of the interconnect is connected to an Aurora core slave AXI-S. The master AXI-S i/f of the Aurora is connected to a block called VDF router, which demuxes the streaming traffic and sends it to each of the slave AXI-S i/fs of RRA, VFP and VT. 

The top level of the design is an IP Integrator block diagram. I've added a System ILA into the BD to monitor 4 of the AXI-S interfaces as follows: 

Slot 0: RRA Master to AXI Interconnect Slave. 
Slot 1: AXI Interconnect Master to Aurora Slave.
Slot 2: VDF_Router Master (RRA) to RRA Slave
Slot 2: VDF_Router Master  (VDF) to VDF Slave:

Here's a screen shot of the ILA window in the Hardware Manager:

System ILA label bug.png

Now the over all interface label for slot 0 is correct, but the TVALID label is incorrect--this is not the VDF Router to VFP interface TVALID signal. The TREADY signal is labled correctly. The tlast and tdata have switched nomenclature and show the signal hierarchy rather than referring to the slot and interface.
For slot 1, the interconnect label is correct, but the individual signals are all incorrect. This is the interface between the AXIS Interconnect block and the Aurora--it is not connected to the VFP at all. 
For slot 2m the interface label is correct but all the signals are wrong again. This is the interface from the VDF router to the RRA and not connected to the VT block at all. 
Finally for slot 3. This is the vfd router to VFP interface, but all the signals are wrong, this isn't part of the interfaces to the VT block. 
Now I did consider corruption, so I ripped out the System ILA last night, rebuilt the BD, added back in the ILA, rebuilt the BD again and finally rebuilt the FPGA. But it this didn't fix the issue. I really don't know where to go looking for the corruption, and I'm not sure if rebuilding the BD from scratch would fix anything or not. 

I have confirmed that at least slot 0 and slot 1 appear to be monitoring the correct signals and I'm seeing the expected behaviour. So this looks like a labeling issue rather than an actual routing problem. 

I haven't been able to find any other references to this in the forums. Does anyone know of a good way to clear out the corruption and force Vivado to put down the proper labels? It's difficult to use the System ILA when it labels most of the signals incorrectly. 

I am currently using Vivado 2018.3

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Registered: ‎02-09-2017

Hi @barrygmoss,


Thank you for the detailed explanation.

Just so I can better understand your design flow, how are you creating the design? Is it IPI (Block Design) or just traditional RTL instantiation?

How are you adding the ILA to the design (using IPI, using IP Catalog, using Setup Debug Wizard, or using TCL commands)?

The first request I'd like to make is for you to take a look at the .ltx file (normally you point to it at the same time you load the bitstream).

If you open that file with a text editor, do you see the same namings for the probes and inidividual signals? If you can, please also share the ltx file here so I can look into it as well.

If the ltx file contains the same structure, Vivado might be mixing it up / renaming probes at implementation time and we might have to apply some constraints to the nets to force it to not rename or reorganize it. Basically, you'd add the constraint set_property DONT_TOUCH 1 [get_nets [get_property PARENT <net marked for debug> ] ] and the run Synthesis and Implementation again.

You can also open the Synthesized design and run the command write_debug_probes my_probes.ltx. You can compare that LTX file to the old one and see if it contains the correct naming and order. You can also use that file when programming the bitstream and see if the ILA probes are shown with the correct names.

Please let us know about the outcomes for the tests above.


Thank you,

Andre Guerrero

Product Applications Engineer

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