03-29-2020 05:00 AM
Why doesn't ILA show the enumeration values of an SystemVerilog `enum` variable?
Intel's Quartus SignalTap is able to do that automatically, why not Xilinx's ILA?
04-07-2020 05:56 PM
It seems Vivado currently cannot do that automatically from SystemVerilog, but the feature is available via TCL commands in the ILA GUI.
Please take a look at the document Tcl Command Reference Guide - UG835 (v2019.2), pg. 52.
I know it's a bit of extra work, but once you've done that once (via the GUI), these settings will be saved in your project and should show up automatically in subsequent users.
You can also create a TCL script that you can run on this project and reuse on other projects as well.
05-05-2020 07:48 AM
That isn't exactly true. I have been using system verilog for several years now and Vivado is usually quite good at automatically populating the ltx (debug probes) file with the enumerated names and their matching values.
Unfortunately I now have some cases which do NOT automatically populate the enumerations and I don't understand why. I'm using Vivado 2019.2.
At what stage is the ltx file created? Is there something we can look at to see why it might be failing to automatically get the enumerations in some cases?
05-11-2020 08:13 AM
I'm currently using Vivado 2019.2. I didn't use 2019.1 for long so I can't comment on that much. But prior to this using 2018 versions for a long while I NEVER had this enumeration issue. This seems to indicate that this is either a bug or there is somehow new criteria to meet in order for Vivado to automatically recognize the enumeration list.
Can someone from Xilinx please comment on if this is already a known issue staged to be corrected in Vivado 2020.1?