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Adventurer
Adventurer
14,098 Views
Registered: ‎07-27-2011

Tandem PCIe programming issue

I am having an issue with programming the KC705 BPI PROM with the PCIe core example using tandem PCIe. When I program the first file to the KC705 the done bit does not get set.

I am using the BPI prom and using Impact 14.7. The build was done in Vivado 2014.2. I am using  pg054-7series-pcie June 4,2014 as a guide.

I was successful programming the spi PROM but the host system just power cycled.

I have successfully used the BPI PROM for other non-tandem PCIe  designs.

Any help would be much apperceived.

 

Thanks

 

John

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10 Replies
Community Manager
Community Manager
14,096 Views
Registered: ‎07-23-2012

Re: Tandem PCIe programming issue

Hi John,

Were you able to program the BPI successfully? Was the fpga not getting configured with the image stored in BPI flash?

If yes, can you please read the status register of the fpga after configuration failure and share it here.

Were you able to program the fpga with the tandem bit file in jtag mode?

Regards,
Krishna
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Adventurer
Adventurer
14,082 Views
Registered: ‎07-27-2011

Re: Tandem PCIe programming issue

For some reason I won't let me post with an attachment.

I am using the Digilent JTAG cable to program the prom

 

The text below is form the impact console during programming and verification

 

 

 

 

// *** BATCH CMD : setCable -port auto

INFO:iMPACT - Digilent Plugin: Plugin Version: 2.4.4

INFO:iMPACT - Digilent Plugin: found 1 device(s).

INFO:iMPACT - Digilent Plugin: opening device: "JtagSmt1", SN:210203337506

INFO:iMPACT - Digilent Plugin: User Name: JtagSmt1

INFO:iMPACT - Digilent Plugin: Product Name: Digilent JTAG-SMT1

INFO:iMPACT - Digilent Plugin: Serial Number: 210203337506

INFO:iMPACT - Digilent Plugin: Product ID: 30800151

INFO:iMPACT - Digilent Plugin: Firmware Version: 0109

INFO:iMPACT - Digilent Plugin: JTAG Port Number: 0

INFO:iMPACT - Digilent Plugin: JTAG Clock Frequency: 10000000 Hz

Attempting to identify devices in the boundary-scan chain configuration...

INFO:iMPACT - Current time: 6/16/2014 12:05:57 PM

// *** BATCH CMD : Identify -inferir

PROGRESS_START - Starting Operation.

Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc7k325t, Version : 3

INFO:iMPACT:1777 -

Reading D:/Xilinx/14.7/ISE_DS/ISE/kintex7/data/xc7k325t.bsd...

INFO:iMPACT - Using CseAdapterBSDevice

INFO:iMPACT:501 - '1': Added Device xc7k325t successfully.

----------------------------------------------------------------------

----------------------------------------------------------------------

done.

PROGRESS_END - End Operation.

Elapsed time =      0 sec.

// *** BATCH CMD : identifyMPM

Selected part: 28F00AP30

// *** BATCH CMD : attachflash -position 1 -bpi "28F00AP30"

// *** BATCH CMD : assignfiletoattachedflash -position 1 -file "C:/EntropyDesign/Boston_Scientific/KC705_Tan_14_2/pcie_X4_gen1_Tandem_example/pcie_X4_gen1_Tandem_example.runs/impl_1/KC705_PCIe_Tan1.mcs"

INFO:iMPACT - Current time: 6/16/2014 12:07:29 PM

// *** BATCH CMD : Program -p 1 -dataWidth 16 -rs1 NONE -rs0 NONE -bpionly -e -v -loadfpga

PROGRESS_START - Starting Operation.

Maximum TCK operating frequency for this device chain: 66000000.

Validating chain...

Boundary-scan chain validated successfully.

1: Device Temperature: Current Reading:   27.73 C, Min. Reading:   25.77 C, Max. Reading:   28.23 C

1: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.996 V, Max. Reading:   0.999 V

1: VCCAUX Supply: Current Reading:   1.805 V, Min. Reading:   1.802 V, Max. Reading:   1.811 V

Core is not loaded.

BPI SLAVE TYPE in Cse_Operate.c is 0

INFO:iMPACT - Downloading D:\Xilinx\14.7\ISE_DS\ISE\data\cse\cseflash\kintex7\xc7k325t_xsdbbpi.cor core file.

INFO:iMPACT - Creating XC7K325T device.

PROGRESS_START - Starting Operation.

'1': Programming device...

 Match_cycle = NoWait.

Match cycle: NoWait

 LCK_cycle = NoWait.

LCK cycle: NoWait

done.

INFO:Cse - Status register values:

INFO:Cse - 0011 1111 0101 1110 0000 1000 0100 0010

INFO:Cse - '1': Completed downloading bit file to device.

INFO:Cse - '1': Programming completed successfully.

PROGRESS_END - End Operation.

Elapsed time =      1 sec.

key: period_frc, value: 0

key: dclk_has_reset, value: 0

key: period_int, value: 10

Found Slave on Bus Index.

Found Slave on Bus Index.

Slave Int Type is 83, Slave Index is -1, BPI_SLAVE is 83

Slave Type is 83, Slave Index is 0

PROGRESS_START - Starting Operation.

Reset Core

Reset Core

Set Data Width

Setting Flash Control Pins ...

Populating BPI common flash interface ...

Common Flash Interface Information Query completed successfully.

INFO:Cse - Common Flash Interface Information from Device:

INFO:Cse - Verification string:          51 52 59

INFO:Cse - Manufacturer ID:             89

INFO:Cse - Vendor ID:                      01

INFO:Cse - Device Code:                   1b

Reset Core

Using x16 mode ...

Set Data Width

Setting Flash Control Pins ...

'1': Erasing device...

'1': Start address = 0x00000000, End address = 0x000C14EB.

done.

'1': Erasure completed successfully.

Reset Core

Using x16 mode ...

Set Data Width

Setting Flash Control Pins ...

INFO:Cse - Using Buffered Programming.

'1': Programming Flash.

done.

'1': Flash Programming completed successfully.

Reset Core

Using x16 mode ...

Set Data Width

Setting Flash Control Pins ...

'1': Reading device contents...

done.

'1': Verification completed.

PROGRESS_END - End Operation.

Elapsed time =     28 sec.

'1': Configuration data download to FPGA was not successful. DONE did not go high, please check your configuration setup and mode settings.

 

 

Hope this helps 

 

Thanks

 

John

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Community Manager
Community Manager
14,077 Views
Registered: ‎07-23-2012

Re: Tandem PCIe programming issue

Hi John,

This log shows that the flash was successfully programmed.

Can you please share the status register log of the fpga as requested in my previous post?

To read the status register, please follow the below steps in impact-

1. Select the device.
2. Go to Debug-> Read Device Status

Also, were you able to configure the fpga with the .bit file in JTAG mode? If you are unable to then there could be an issue with the bit file and in any case, the status register will give us a clue.

Regards,
Krishna
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Adventurer
Adventurer
14,074 Views
Registered: ‎07-27-2011

Re: Tandem PCIe programming issue

Hi Krishna,

 

 

The following two FPGA status dumps listed below. The first is down loading to BPI and the second is loading the FPGA directly using the .bit file

The BPI Flash did not generate a done status and the direct FPGA load worked.  

 

 

 

 

Status of FPGA down loading to BPI PROM

 

INFO:iMPACT - Current time: 6/17/2014 7:56:51 AM

// *** BATCH CMD : ReadStatusRegister -p 1

Maximum TCK operating frequency for this device chain: 66000000.

Validating chain...

Boundary-scan chain validated successfully.

1: Device Temperature: Current Reading:   26.75 C, Min. Reading:   22.32 C, Max. Reading:   27.24 C

1: VCCINT Supply: Current Reading:   0.996 V, Min. Reading:   0.996 V, Max. Reading:   0.999 V

1: VCCAUX Supply: Current Reading:   1.805 V, Min. Reading:   1.802 V, Max. Reading:   1.811 V

'1': Reading bootsts register contents...

[0] VALID_0 - ERROR OR END OF STARTUP (EOS) DETECTED                       :         1

[1] FALLBACK_0 - FALLBACK TRIGGERED RECONFIGURATION                        :         0

[2] IPROG_0 - INTERNAL WARMBOOT (IPROG) TRIGGERED RECONFIGURATION          :         0

[3] WTO_ERROR_0 - WATCHDOG TIME OUT ERROR                                  :         0

[4] ID_ERROR_0 - FPGA DEVICE IDCODE ERROR                                  :         0

[5] CRC_ERROR_0 - CYCLIC REDUNDANCY CHECK (CRC) ERROR                      :         0

[6] WRAP_ERROR_0 - BPI FLASH ADDRESS COUNTER WRAP AROUND ERROR             :         1

[7] HMAC_ERROR_0 - HMAC ERROR                                              :         0

[8] VALID_1 - ERROR OR END OF STARTUP (EOS) DETECTED                       :         0

[9] FALLBACK_1 - FALLBACK TRIGGERED RECONFIGURATION                        :         0

[10] IPROG_1 - INTERNAL WARMBOOT (IPROG) TRIGGERED RECONFIGURATION         :         0

[11] WTO_ERROR_1 - WATCHDOG TIME OUT ERROR                                 :         0

[12] ID_ERROR_1 - FPGA DEVICE IDCODE ERROR                                 :         0

[13] CRC_ERROR_1 - CYCLIC REDUNDANCY CHECK (CRC) ERROR                     :         0

[14] WRAP_ERROR_1 - BPI FLASH ADDRESS COUNTER WRAP AROUND ERROR            :         0

[15] HMAC_ERROR_1 - HMAC ERROR                                             :         0

'1': Reading status register contents...

[0] CRC ERROR                                                              :         0

[1] DECRYPTOR ENABLE                                                       :         0

[2] PLL LOCK STATUS                                                        :         1

[3] DCI MATCH STATUS                                                       :         1

[4] END OF STARTUP (EOS) STATUS                                            :         0

[5] GTS_CFG_B STATUS                                                       :         0

[6] GWE STATUS                                                             :         0

[7] GHIGH STATUS                                                           :         0

[8] MODE PIN M[0]                                                          :         0

[9] MODE PIN M[1]                                                          :         1

[10] MODE PIN M[2]                                                         :         0

[11] INIT_B INTERNAL SIGNAL STATUS                                         :         1

[12] INIT_B PIN                                                            :         0

[13] DONE INTERNAL SIGNAL STATUS                                           :         0

[14] DONE PIN                                                              :         0

[15] IDCODE ERROR                                                          :         0

[16] SECURITY ERROR                                                        :         0

[17] SYSTEM MONITOR OVER-TEMP ALARM STATUS                                 :         0

[18] CFGSTARTUPSTATE MACHINE PHASE                                       :         0

[19] CFGSTARTUPSTATE MACHINE PHASE                                       :         0

[20] CFGSTARTUPSTATE MACHINE PHASE                                       :         0

[21] RESERVED                                                              :         0

[22] RESERVED                                                              :         0

[23] RESERVED                                                              :         0

[24] RESERVED                                                              :         0

[25] CFG BUS WIDTH DETECTION                                               :         0

[26] CFG BUS WIDTH DETECTION                                               :         1

[27] HMAC ERROR                                                            :         0

[28] PUDC_B PIN                                                            :         0

[29] BAD PACKET ERROR                                                      :         1

[30] CFGBVS PIN                                                            :         1

[31] RESERVED                                                              :         0

 

Status of FPGA downloading .bit file directly to FPGA

 

 

INFO:iMPACT - Current time: 6/17/2014 8:19:10 AM

// *** BATCH CMD : ReadStatusRegister -p 1

Maximum TCK operating frequency for this device chain: 66000000.

Validating chain...

Boundary-scan chain validated successfully.

1: Device Temperature: Current Reading:   27.24 C, Min. Reading:   25.27 C, Max. Reading:   27.24 C

1: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.996 V, Max. Reading:   0.999 V

1: VCCAUX Supply: Current Reading:   1.808 V, Min. Reading:   1.802 V, Max. Reading:   1.808 V

'1': Reading bootsts register contents...

[0] VALID_0 - ERROR OR END OF STARTUP (EOS) DETECTED                       :         1

[1] FALLBACK_0 - FALLBACK TRIGGERED RECONFIGURATION                        :         0

[2] IPROG_0 - INTERNAL WARMBOOT (IPROG) TRIGGERED RECONFIGURATION          :         0

[3] WTO_ERROR_0 - WATCHDOG TIME OUT ERROR                                  :         0

[4] ID_ERROR_0 - FPGA DEVICE IDCODE ERROR                                  :         0

[5] CRC_ERROR_0 - CYCLIC REDUNDANCY CHECK (CRC) ERROR                      :         0

[6] WRAP_ERROR_0 - BPI FLASH ADDRESS COUNTER WRAP AROUND ERROR             :         0

[7] HMAC_ERROR_0 - HMAC ERROR                                              :         0

[8] VALID_1 - ERROR OR END OF STARTUP (EOS) DETECTED                       :         0

[9] FALLBACK_1 - FALLBACK TRIGGERED RECONFIGURATION                        :         0

[10] IPROG_1 - INTERNAL WARMBOOT (IPROG) TRIGGERED RECONFIGURATION         :         0

[11] WTO_ERROR_1 - WATCHDOG TIME OUT ERROR                                 :         0

[12] ID_ERROR_1 - FPGA DEVICE IDCODE ERROR                                 :         0

[13] CRC_ERROR_1 - CYCLIC REDUNDANCY CHECK (CRC) ERROR                     :         0

[14] WRAP_ERROR_1 - BPI FLASH ADDRESS COUNTER WRAP AROUND ERROR            :         0

[15] HMAC_ERROR_1 - HMAC ERROR                                             :         0

'1': Reading status register contents...

[0] CRC ERROR                                                              :         0

[1] DECRYPTOR ENABLE                                                       :         0

[2] PLL LOCK STATUS                                                        :         1

[3] DCI MATCH STATUS                                                       :         1

[4] END OF STARTUP (EOS) STATUS                                            :         1

[5] GTS_CFG_B STATUS                                                       :         1

[6] GWE STATUS                                                             :         1

[7] GHIGH STATUS                                                           :         1

[8] MODE PIN M[0]                                                          :         0

[9] MODE PIN M[1]                                                          :         1

[10] MODE PIN M[2]                                                         :         0

[11] INIT_B INTERNAL SIGNAL STATUS                                         :         1

[12] INIT_B PIN                                                            :         1

[13] DONE INTERNAL SIGNAL STATUS                                           :         1

[14] DONE PIN                                                              :         1

[15] IDCODE ERROR                                                          :         0

[16] SECURITY ERROR                                                        :         0

[17] SYSTEM MONITOR OVER-TEMP ALARM STATUS                                 :         0

[18] CFGSTARTUPSTATE MACHINE PHASE                                       :         0

[19] CFGSTARTUPSTATE MACHINE PHASE                                       :         0

[20] CFGSTARTUPSTATE MACHINE PHASE                                       :         1

[21] RESERVED                                                              :         0

[22] RESERVED                                                              :         0

[23] RESERVED                                                              :         0

[24] RESERVED                                                              :         0

[25] CFG BUS WIDTH DETECTION                                               :         1

[26] CFG BUS WIDTH DETECTION                                               :         0

[27] HMAC ERROR                                                            :         0

[28] PUDC_B PIN                                                            :         0

[29] BAD PACKET ERROR                                                      :         0

[30] CFGBVS PIN                                                            :         1

[31] RESERVED                                                              :         0

 

 

 

Thanks 

 

John

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Community Manager
Community Manager
14,070 Views
Registered: ‎07-23-2012

Re: Tandem PCIe programming issue

Hi John,

This looks strange. In the first case (FPGA configured from BPI), you were seeing a bad packet error; it means that the bit file is corrupt.

Can you please run the verify operation on the BPI flash again?

If possible, share the bit file with me. I'll try to reproduce it at my end on a KC705 board.

Regards,
Krishna
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Adventurer
Adventurer
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Registered: ‎07-27-2011

Re: Tandem PCIe programming issue

 

Hi Krishna,

 

Thanks for moving the thread back.

 

 

I ran a verification on the prom in KC705 and got the following output on the console:

 

INFO:iMPACT - Current time: 6/19/2014 9:06:29 AM

// *** BATCH CMD : Verify -p 1 -bpionly

PROGRESS_START - Starting Operation.

Maximum TCK operating frequency for this device chain: 66000000.

Validating chain...

Boundary-scan chain validated successfully.

1: Device Temperature: Current Reading:   28.23 C, Min. Reading:   27.73 C, Max. Reading:   29.21 C

1: VCCINT Supply: Current Reading:   0.996 V, Min. Reading:   0.993 V, Max. Reading:   0.999 V

1: VCCAUX Supply: Current Reading:   1.805 V, Min. Reading:   1.799 V, Max. Reading:   1.808 V

Core is not loaded.

BPI SLAVE TYPE in Cse_Operate.c is 83

INFO:iMPACT - Downloading D:\Xilinx\14.7\ISE_DS\ISE\data\cse\cseflash\kintex7\xc7k325t_xsdbbpi.cor core file.

INFO:iMPACT - Creating XC7K325T device.

PROGRESS_START - Starting Operation.

'1': Programming device...

 Match_cycle = NoWait.

Match cycle: NoWait

 LCK_cycle = NoWait.

LCK cycle: NoWait

done.

INFO:Cse - Status register values:

INFO:Cse - 0011 1111 0101 1110 0000 1000 0100 0010

INFO:Cse - '1': Completed downloading bit file to device.

INFO:Cse - '1': Programming completed successfully.

PROGRESS_END - End Operation.

Elapsed time =      2 sec.

key: period_frc, value: 0

key: dclk_has_reset, value: 0

key: period_int, value: 10

Found Slave on Bus Index.

Found Slave on Bus Index.

Slave Int Type is 83, Slave Index is 0, BPI_SLAVE is 83

Slave Type is 83, Slave Index is 0

PROGRESS_START - Starting Operation.

Reset Core

Reset Core

Set Data Width

Setting Flash Control Pins ...

Populating BPI common flash interface ...

Common Flash Interface Information Query completed successfully.

INFO:Cse - Common Flash Interface Information from Device:

INFO:Cse - Verification string:    51 52 59

INFO:Cse - Manufacturer ID:       89

INFO:Cse - Vendor ID:                01

INFO:Cse - Device Code:            1b

Reset Core

Using x16 mode ...

Set Data Width

Setting Flash Control Pins ...

'1': Reading device contents...

done.

'1': Verification completed.

PROGRESS_END - End Operation.

Elapsed time =      8 sec.

 

It looks as if the device gets reprogrammed when a verification is performed.

 

Also I have attached the bin, bit, and mcs files tha were used for programming. 

 

Thanks 

 

John

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Adventurer
Adventurer
13,996 Views
Registered: ‎07-27-2011

Re: Tandem PCIe programming issue

Hi Krishna, 

 

Any update on the KC705 tandem procramming files that I sent.

 

Thanks 

 

John

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Community Manager
Community Manager
13,993 Views
Registered: ‎07-23-2012

Re: Tandem PCIe programming issue

Hi John,

I didn't get a chance to try the files that you shared. I would do it today and update the thread.

Regards,
Krishna
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Adventurer
Adventurer
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Registered: ‎07-27-2011

Re: Tandem PCIe programming issue

Hi Krishna,

 

I neglected to put the emcclk pin in the top level file and constraints.

 

When I rebuilt it the KC705 the done bit went active. Although now when I power up my PC with the KC705 the system just power cycles.

I don't think this is hardware issue as I have loaded my non tandem design with PCIe and it works.

 

Basically this design is the example design generated from the Xilinx Vivado tool with PCIe tandem enabled in the IP GUI.

 

Attached is the bit and mcs files form that build. Could you try it on your KC705 and let me know if you have the same power cycling issues.

 

 

Thanks

 

John

Newbie wangjixin
Newbie
101 Views
Registered: ‎12-17-2019

Re: Tandem PCIe programming issue

How did you solve this problem in the end please?

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