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Anonymous
Not applicable
549 Views

There are no debug cores

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Hi All,

I've implemented my project and generated the bit stream. I've added some debug cores, and I am able to see the green symbols in the debug cores over signals on the block design attached. When I connect to the device through hardware manager, it says "there are no debug cores" and I cannot see ILA waveforms!

The warning messages I am getting:

INFO: [Labtools 27-1434] Device xc7z020 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-3403] Dropping logic core with cellname:'design_1_i/ila_3' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-3403] Dropping logic core with cellname:'u_ila_0' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-3403] Dropping logic core with cellname:'design_1_i/ila_4' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-3403] Dropping logic core with cellname:'design_1_i/ila_1' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-3403] Dropping logic core with cellname:'design_1_i/ila_2' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-3403] Dropping logic core with cellname:'design_1_i/ila_0' from probes file, since it cannot be found on the programmed device.

How can I solve this problem? Many thanks..

Error_ila.png
Error_ila2.png
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1 Solution

Accepted Solutions
Moderator
Moderator
502 Views
Registered: ‎11-09-2015

Re: There are no debug cores

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Hi @Anonymous ,

I see that you are on zynq. A common mistake is to forgot to set up the zynq thus the clock are not available for the ILA.

What you can do: start your application in debug mode in SDK (or use the hello world application). When the debug is stopped at the main entry, program the FPGA.

The clock from the zynq should be available and you should then see the ILAs.

Hope that helps,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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4 Replies
Xilinx Employee
Xilinx Employee
539 Views
Registered: ‎05-22-2018

Re: There are no debug cores

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Hi @Anonymous ,

Please check the below AR# link, might be helpful:

https://www.xilinx.com/support/answers/64764.html

Thanks,

Raj

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Anonymous
Not applicable
526 Views

Re: There are no debug cores

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Hi Dear  

I've checked it. But, for the first solution, can you plz tell how it is to check if the clock is a non-free-running clock or not? Thanks..

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Moderator
Moderator
503 Views
Registered: ‎11-09-2015

Re: There are no debug cores

Jump to solution

Hi @Anonymous ,

I see that you are on zynq. A common mistake is to forgot to set up the zynq thus the clock are not available for the ILA.

What you can do: start your application in debug mode in SDK (or use the hello world application). When the debug is stopped at the main entry, program the FPGA.

The clock from the zynq should be available and you should then see the ILAs.

Hope that helps,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Anonymous
Not applicable
495 Views

Re: There are no debug cores

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Thank you dear florentw . When I run any application in Xilinx SDK, it produces the clock signals, and then I see all the debug cores in FPGA HW manager. 

Many thanks,

 

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