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hjs
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Registered: ‎04-06-2021

Unwanted signal delay

Hi, 

I used RTL simulator to simulate the behavior of a small piece of verilog code in vivado 2020.1. As shown below, I found that there is a delay when signal propagate from s_axis_tvalid(top one) to s_axis_tvalid(bottom one). However it is not expected as the top one is test bench generated signal and it is just passed to the bottom on which the hardware module. Is it due to any settings? Because the code is quite simple, I did not find anything wrong. And my last project using vivado 2019.1 but I did not have such observation. Is there any setting I should config?

hjs_1-1626243457042.png

 

Regards!

JS

 

 

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dpaul24
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Registered: ‎08-07-2014

@hjs ,

From the TB, you are driving tvalid high at the falling edge of the clock. This should not be done, drive the signals at rising clock edges.

Now your DUT is a sequential design, so the tvalid is registered only at the next rising clock edge and hence you see the delay.

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hjs
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Registered: ‎04-06-2021

Hi, @dpaul24 

Thank you for your reply. But I am still have some doubt about it. I pasted my test bench code as below. In the test bench, I just define s_axis_tvalid as a register and it is not synchronize with any clock. In my previous post, the top s_axis_tvalid is the generated from initial block and I forced to changed to 1 at some time (as my last post at the falling clock edge). The bottom s_axis_tvalid should be the input to the dummy_test. My understanding is that both s_axis_tvalid should be the identical signal and they should rise and fall at the same time in the waveform. This is the part that I don't understand why the bottom one follows the rising clock edge.

`timescale 1ns/100ps

module dummy_test;

reg clk;
reg rst;
reg[47:0] input_data;
wire[47:0] output_data;
reg s_axis_tvalid;
wire s_axis_tready;
wire m_axis_tvalid;
reg m_axis_tready;

always  #5 clk= !clk;

initial 
begin
    clk = 0;
    rst = 1;
    input_data = 48'h000000;
    m_axis_tready = 0;
    s_axis_tvalid = 0;
    #10 rst = 0;
    #10 rst = 1;
    
end

dummy_test test(clk, 
                    rst,
                    input_data,
                    s_axis_tvalid,
                    s_axis_tready,
                    output_data,
                    m_axis_tvalid,
                    m_axis_tready
                    );



endmodule

 

 

 

 

 

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dpaul24
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Registered: ‎08-07-2014

@hjs ,

It seems you did not post the complete code.

In the above post I can see only the clock and reset toggling. Where are the AXIS signals being driven?

It is likely that you have explicitly not modeled for tvalid to go high on the falling edge of the clock. But it might be that you have inserted delays after which signals go high or low.

So the solution here is to make tvalid go high after another half clock-period delay. That would be the next clock rising edge. Apply this to the part of the TB code where you are driving tvalid high.

btw - Driving the AXIS signals from a clocked process (also inside a TB) is recommended, they are all synchronous.

 

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