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Observer flosch
Observer
7,233 Views
Registered: ‎11-14-2012

Using Core Inserter - signals have been synthesized away?

Hey guys,

 

I am working with a USRP from Ettus Research which has got a Spartan-3A DSP in it. I try to implement a custom module in their verilog code and I am encountering problems in debugging my code using a Xilinx Platform Cable II and the ChipScope Core Inserter (ISE 12.1 for now).

The problem is that I can't find the signals in the Net List of the Core Inserter. I had a look at my custom block in the RTL Schematics (Technology is the same) and can't find the signals in the Net List (e.g. the signal bb_sample). See the screenshot below:

 

Screenshot-1.png

 

(if it is too small, see attachment)

 

I was already searching the forum and hit on the following approaches:

1. Keep Hierarchy: Yes

2. SAVE NET FLAG: added the following in before my custom module:

(* S = "TRUE" *)
module custom_dsp_rx
( ...

PLUS added: NET "*" S=TRUE; to my .ucf file

3. analyzed the synthesize report and tried to find "bb_sample" -> negative

 

How can I get the input/output signals of my custom block connected and debugged in Core Inserter?

 

Thanks in advance! Cheers, Flo

 

Screenshot-1.png
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3 Replies
Observer flosch
Observer
7,231 Views
Registered: ‎11-14-2012

Re: Using Core Inserter - signals have been synthesized away?

the screenshot still appears in the same size in the attachment. see here to enlarge it.

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Professor
Professor
7,219 Views
Registered: ‎08-14-2007

Re: Using Core Inserter - signals have been synthesized away?

It's possible that the nets are still in the design, but you have not found them yet.

In the Chipscope inserter "Select Net" dialog box, select the top of the hierarchy

to get all of the nets in the design.  In your posted screen shot, you have apparently

selected the "u2plus_core" which only contains nets from the core's .ngc netlist.

 

With all nets in the signal list, use the "Pattern" box to search for "*bb_sample*"

to allow for hiearchy at the start and subscripts at the end.  If you still can't find these

nets there's one more possibility.

 

In a hierarchical design, nets that travel through the hirarchy on module ports can

have different names at each level of the hierarchy.  Generally, XST uses the name

at the driving register, which can be at a lower level in the hierarchy than the net

name you're trying to match.

 

-- Gabor

 

PS - don't worry about the image.  If you right click and select "view image," at least

in FireFox, you can see it at full resolution.

-- Gabor
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Observer flosch
Observer
7,198 Views
Registered: ‎11-14-2012

Re: Using Core Inserter - signals have been synthesized away?


@gszakacs wrote:

It's possible that the nets are still in the design, but you have not found them yet.

In the Chipscope inserter "Select Net" dialog box, select the top of the hierarchy

to get all of the nets in the design.  In your posted screen shot, you have apparently

selected the "u2plus_core" which only contains nets from the core's .ngc netlist.

 


Yes, thought about the same. I should have mentioned it but under the top module u2plus there are only the top primitives.

 


In a hierarchical design, nets that travel through the hirarchy on module ports can

have different names at each level of the hierarchy.  Generally, XST uses the name

at the driving register, which can be at a lower level in the hierarchy than the net

name you're trying to match.



That would make sense and should be the solution. By that, I conclude that only the used pins are being remained after synthesize and the unused ones being optimized away. Anyway, that make it even more difficult to me to debug the whole design or getting some more insights about what is happening inside the existing system during runtime.

I think I will rather take the bottom-top approach and verify the functionality of my custom module using the ISim simulator.

 

Thanks for your help! Cheers,Flo

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