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Observer
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Registered: ‎05-04-2016

Using XVC and Debug bridge to chipscope a local Zynq design

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I have found resources that will let me:

  1. Turn a microzed into an expensive JTAG cable. (xapp1251)
  2. Use PCIe to debug a locally connected FPGA. (video)

What I haven't found is a driver/program that will let me run xvcserver on a Zynq to debug a design on the same chip.  Does such a thing exist?  Or do I have to modify one of the previously mentioned examples to implement this myself?  We actually did try to adapt xapp1251 to allow the ARM to drive JTAG for the FPGA, but it locks at some point so I think that is a deadend. 

This seems like an obvious application, so I am perplexed by the lack of an examples.

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Observer
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Registered: ‎05-04-2016

Re: Using XVC and Debug bridge to chipscope a local Zynq design

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Okay. Sounds like the non-PCIe version is still using the UIO driver.  Are there plans to create a custom driver/device node for the non-PCIe version?

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Registered: ‎02-09-2017

Re: Using XVC and Debug bridge to chipscope a local Zynq design

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Hi @derrickg,

 

That's a great question. We are actually working on a new XAPP (similar to the XAPP1251) that will use a MPSoC and have more use cases, such as the one you've mentioned.

You definitely can do that configuration, and you will need to know how to use the Petalinux to create a bootable image to place on a SD card and boot the PS side of the Zynq.

As an example, you'd create the configuration as below, using the Debug Bridge IP.

XVC_Zynq_image.png

In Block Design, that diagram would translate as something like this (there' some extra IP's such as a counter, just to emulate a logic and allow us to use the ILA).

XVC_Zynq_Block_Design.png

Observe the PS talks via AXI to an AXI Interconnect, which talks to the Debug Bridge (in AXI to BSCAN mode), which talks to the ILA/VIO via BSCAN.

From here, you'd need to generate bitstream and Export Hardware including bitstream.

Now, with the hdf file that has been generated by the export, you can use Petalinux to create a Linux Embedded image for the Zynq (Similar process as explained in the XAPP1251, pg. 11).

 

The following page has more resources on how to use the Petalinux and examples:

https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0016-petalinux-tools-hub.html

 

Please let me know if you have any questions.

Thanks,

Andre Guerrero

Product Applications Engineer

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Registered: ‎05-04-2016

Re: Using XVC and Debug bridge to chipscope a local Zynq design

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Thanks for those diagrams.  That gives me confidence that I have things hooked up right.

I actually haven't ever used peta linux, as we chose to go with Arch several years ago.  Does peta linux have a version of xvcserver that can talk to the debug bridge?  What kernel driver is it using?  I grep'ed the xilinx-2018.2 version of the kernel code and didn't see a 'compatible' string that matched the one in the generated device tree. The closest I have found to a kernel driver was the PCIe one.  I could probably hack it to strip out all of the PCIe stuff and make it a platform driver instead, but if there is already one available then I don't want to go down that rabbit hole.

 

 

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Registered: ‎02-09-2017

Re: Using XVC and Debug bridge to chipscope a local Zynq design

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Hi @derrickg,

 

it does not include the XVC application by default. While creating the Petalinux image, you must include the XVC application file in it.

The file is already included in the example design package that you download from the XAPP1251. From the instructions on how to create the Petalinux Image, on step 3 you can see where a template.c file is replaced by the xvcServer.c file, in order to enable such feature.

petalinux_XVC_server.JPG

You can also download the xvcServer.c file from Xilinx Github: https://github.com/Xilinx/XilinxVirtualCable

 

 

Andre Guerrero

Product Applications Engineer

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Registered: ‎05-04-2016

Re: Using XVC and Debug bridge to chipscope a local Zynq design

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Okay. Sounds like the non-PCIe version is still using the UIO driver.  Are there plans to create a custom driver/device node for the non-PCIe version?

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Re: Using XVC and Debug bridge to chipscope a local Zynq design

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I was able to get xvcServer working, which is awesome.  Now I am trying to debug an issue that causes the ARM to crash.  It appears that if I select Bypass-mode that I should be able to swap between the soft bscan and the hard JTAG so that I can run JTAG on a processor that doesn't crash.  How to I switch between internal and external JTAG?

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Registered: ‎05-17-2018

Re: Using XVC and Debug bridge to chipscope a local Zynq design

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Hi Andre,

 

I'm recently working on making XVC server running on arm in MPSOC. I'm using the debug bridge 3.0 communicating with the arm over AXI LITE (exactly the same way with the figure you posted here). For the software side, I'm using the xapp1251 code. With the new updated AXI LITE register map in PG245, I thought it would be very easy to make it work.

However, now I'm stuck on making arm communicate with the debug bridge. I'm running Ubuntu on the arm, therefore I use "/dev/mem" to access the physical memory where debug bridge was mapped to. But every time when I tried to write something to the debug bridge AXI LITE registers, the arm core would hang immediately.

I wonder do you have any clue of what's happening? Or it would be even better if you can share with me some software reference design regarding running XVC server on arm.

 

Thanks,

Clark

 

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Registered: ‎05-17-2018

Re: Using XVC and Debug bridge to chipscope a local Zynq design

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never mind, I made it work, thanks!
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Re: Using XVC and Debug bridge to chipscope a local Zynq design

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I was pulled off on another project, but was able to get back to this.  It appears that I can use the soft interface until I plug in the hardware JTAG, and then it permanently switches.  This seems to make sense as it defaults to the interface I can use remotely, and automatically (and permanently) switches to hardware interface if that is available.

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Registered: ‎06-27-2018

Re: Using XVC and Debug bridge to chipscope a local Zynq design

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Hello Andre,

how far are you with th XAPP?

Is it possible to use the debug bridge and as  fall back the classical JTAG connection in the Hardware Manager?

I just added the debug bridge with bridge type "AXI to bscan" and enabled the JTAG Fallback Mode. However, I couldnt connect to the ILA via JTAG anymore.

 

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Re: Using XVC and Debug bridge to chipscope a local Zynq design

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For fallback, I had to create two cores. The AXI to BSCAN, then I changed the parameters to allow fallback, which created a m0_bscan output port, then I instatiated a debug bridge and connected to that port.

Inside the AXI to BSCAN there is a big mux that seems to do the switching between external JTAG and the soft bscan.

I tried to do this in 2017.4, but it doesn't work i that version of the IP, so I am waiting for 2019.1 to upgrade and add it to our main project.

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Registered: ‎09-27-2018

Re: Using XVC and Debug bridge to chipscope a local Zynq design

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I'm using Vivado 2018.2 and I'm facing similar issues regarding crashing / hanging / freezing of the ARM Linux application.

We're using a zynq7000 board with linux 4.14 using a yocto system flow related to petalinux. I've implemented the Xilinx XVC driver using the github repo

https://github.com/Xilinx/XilinxVirtualCable , hash: d702f9b7317c1e67ce6070d249dccbb2220192d3

I'm using the kernel driver without any modifications and the user space server with the patch provided in the repo (set listen(fd,5)) to prevent the TCP SYN flooding error. The xvcserver uses IOCTL implementation. The devicetree node adds:

debug_bridge_0@8000000 {
    compatible = "xlnx,xvc";
    reg = <0x80000000 0x10000>;
};

As for the FPGA / PL I've set up an ILA and added a debug-bridge_v3.0 (all using Vivado 2018.2), conected to an AXI Interface (using connection automation, which results in an 1:1 connection).

PL settingPL setting

Anmerkung 2019-11-07 082158.pngAnmerkung 2019-11-07 082354.png

It is obvious to see the debug bridge has exclusive access to the AXI_GP1 interface, PL interfaces all use AXI_GP0 or ACP interface.

 

Even when the user space application is not running, the ARM processor freezes when connecting to the xvc server. It stays connected for a couple of seconds (also with verbose mode) and then freezes. The transmission of the shift operation is usually done (also the handshake to the ioctl device), analyzing the issue with wireshark hasn't given me more information (the client on the windows pc using xsct 2018.2 tries to resend the package, so the server and underlying socket really seems to crash). The console isn't working anymore either ...

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Re: Using XVC and Debug bridge to chipscope a local Zynq design

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After spending much time trying to get it working, I had to remove the soft-bscan and the debug bridge from the design.  If you go this route, you must use a pre-instantiated ILA.  You can't use "MARK_DEBUG" and then wire up the probes programatically after synthesis. :(

Since our workflow is entirely scripted and we rarely open the GUI that was a deal breaker for us.  Until that is fixed, I don't anticipate using the debug bridge with the soft bscan.

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Re: Using XVC and Debug bridge to chipscope a local Zynq design

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In my experience, when the processor crashes that hard, it is usually because some bus transaction didn't finish, and so the entire processor is locked up. This can happen if it accesses some memory address that linux thinks exists, but which actually doesn't, or if a slave doesn't ever respond correctly.
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