03-25-2016 08:36 AM
I tried to verilog code a system using two methods. I synthesized it for Artix - 7. One code was having almost 16 inverter gates less than the other. But still the power report in the implementation section shows the same power reading. Why is it so? Obviously power should reduce if the number of gates decrease. Can anyone helpme?
03-25-2016 09:26 AM
I tried to simply code an AND gate and a NAND gate. But both yield the same power information. In NAND one inverter is an additioal component. So there should be some change in the power report. But no. Y is it so?
03-26-2016 02:08 AM
@raksarian This is not the correct way to do power anlaysis of combinational logic. Design clocks are the main component for dynamic power computation. If no clocks are defined, switching activity estimates will be inaccurate, resulting in inaccurate power
04-28-2016 11:57 PM
@raksarian Did you go through UG907 http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug907-vivado-power-analysis-optimization.pdf to understand the factors and inputs needs for Power Analysis in Vivado?
If not, it may be worthwhile to spend sometime going through UG907 to get a better understanding.
05-02-2017 02:44 AM
While doing the power analysis of combinational circuit, do we need to provide virtual clocks? Anything to be done with edit timing constraints? Also help me in doing the power analysis of a sequential circuit. Where do we specify the clock of the circuit?