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Observer penn
Observer
13,508 Views
Registered: ‎04-02-2014

Virtex-5 "Done" signal is not go high when programmed with JTAG

Hi all,

 

The Done signal is not go high when I programmed the Virtex-5. 

 

In the process of my programming,the Done is low ,that is correct,But the LED flashes once at the program finished,then the LED is in low state.

 

The schematic of mine in the another topic:http://forums.xilinx.com/t5/Design-Tools-Others/Virtex-5-Programming-failed-with-SPI/td-p/478648

 


The program information as follow:

GUI --- Auto connect to cable...
INFO:iMPACT - Connecting to TCF agent...
INFO:iMPACT - Digilent Plugin: Plugin Version: 2.4.4
INFO:iMPACT - Digilent Plugin: no JTAG device was found.
AutoDetecting cable. Please wait.
*** WARNING ***: When port is set to auto detect mode, cable speed is set to default 6 MHz regardless of explicit arguments supplied for setting the baud rates
PROGRESS_START - Starting Operation.
Connecting to cable (Usb Port - USB21).
Checking cable driver.
 Driver file xusbdfwu.sys found.
 Driver version: src=1027, dest=1027.
 Driver windrvr6.sys version = 10.2.1.0. WinDriver v10.21 Jungo (c) 1997 - 2010 Build Date: Aug 31 2010 x86_64 64bit SYS 14:14:44, version = 1021.
 Cable PID = 0008.
 Max current requested during enumeration is 280 mA.
Type = 0x0605.
 Cable Type = 3, Revision = 0.
 Setting cable speed to 6 MHz.
Cable connection established.
Firmware version = 1100.
File version of D:/Xilinx/14.5/ISE_DS/ISE/data/xusbdfwu.hex = 1100.
Firmware hex file version = 1100.
PLD file version = 0012h.
 PLD version = 0012h.
PROGRESS_END - End Operation.
Elapsed time =      1 sec.
Type = 0x0605.
ESN not available for this cable.
Attempting to identify devices in the boundary-scan chain configuration...
INFO:iMPACT - Current time: 2014/6/24 11:30:50
PROGRESS_START - Starting Operation.
Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vlx220, Version : 2
INFO:iMPACT:1777 -
Reading D:/Xilinx/14.5/ISE_DS/ISE/virtex5/data/xc5vlx220.bsd...
INFO:iMPACT:501 - '1': Added Device xc5vlx220 successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
done.
PROGRESS_END - End Operation.
Elapsed time =      0 sec.
'1': Loading file 'D:/Work/FPGA-Project/ddr2/ddr2sdram.bit' ...
done.
INFO:iMPACT:2257 - Startup Clock has been changed to 'JtagClk' in the bitstream stored in memory,
but the original bitstream file remains unchanged.
UserID read from the bitstream file = 0xFFFFFFFF.
INFO:iMPACT:501 - '1': Added Device xc5vlx220 successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
INFO:iMPACT - Current time: 2014/6/24 11:31:06
PROGRESS_START - Starting Operation.
Maximum TCK operating frequency for this device chain: 33000000.
Validating chain...
Boundary-scan chain validated successfully.
1: Device Temperature: Current Reading:   40.04 C, Min. Reading:   38.56 C, Max. Reading:   40.53 C
1: VCCINT Supply: Current Reading:   0.996 V, Min. Reading:   0.993 V, Max. Reading:   0.999 V
1: VCCAUX Supply: Current Reading:   2.493 V, Min. Reading:   2.490 V, Max. Reading:   2.505 V
'1': Programming device...
 Match_cycle = 2.
 LCK_cycle = NoWait.
LCK cycle: NoWait
done.
INFO:iMPACT:2217 - Error shows in the status register, CRC Error bit is NOT 0.
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 1111 1111 1111 1111 1111 1111 1111 1111
INFO:iMPACT:579 - '1': Completed downloading bit file to device.
INFO:iMPACT:188 - '1': Programming completed successfully.
 Match_cycle = 2.
 LCK_cycle = NoWait.
LCK cycle: NoWait
INFO:iMPACT - '1': Checking done pin....done.
'1': Programmed successfully.
PROGRESS_END - End Operation.
Elapsed time =     14 sec.

 

Best Regards.

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21 Replies
Observer penn
Observer
13,507 Views
Registered: ‎04-02-2014

Re: Virtex-5 "Done" signal is not go high when programmed with JTAG

done.png

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Community Manager
Community Manager
13,497 Views
Registered: ‎07-23-2012

Re: Virtex-5 "Done" signal is not go high when programmed with JTAG

Hi Penn,

This looks odd. All the bits in the status register are shown as 1.

Can you please reduce the cable speed and see if the error gets resolved? Do you have another cable? If yes, please try to configure the device using it.

Regards,
Krishna
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Observer penn
Observer
13,493 Views
Registered: ‎04-02-2014

Re: Virtex-5 "Done" signal is not go high when programmed with JTAG

Hi,

 

A thousand thanks for your help.

 

I am a novice,Could you tell me how to reduce the cable speed?

 

Moreover,I config the device with three different cables,but the Done is still in low.

 

Regards.

 

Penn 

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Community Manager
Community Manager
13,490 Views
Registered: ‎07-23-2012

Re: Virtex-5 "Done" signal is not go high when programmed with JTAG

Hi Penn,

 

In the impact, go to Output-> Cable set up as shown in the attached picture.

 

In TCk Speed/Baud rate column, you can reduce the cable speed. 

 

You can refer to http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/pim_db_commsetupdlg.htm for details on cable setup window.

 

Regards,

Krishna 

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Observer penn
Observer
13,488 Views
Registered: ‎04-02-2014

Re: Virtex-5 "Done" signal is not go high when programmed with JTAG

Hi Krishna,

 

Thanks again.

 

I found some trouble about the Done signal.

 

I program the other simple .bit file,the Done signal is correct,but when program the .bit file of my MIG project the Done signal is wrong.

 

Both of the .mcs files were programmed with SPI,the program failed message be shown.

 

Regards.

Penn

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Xilinx Employee
Xilinx Employee
13,486 Views
Registered: ‎07-31-2012

Re: Virtex-5 "Done" signal is not go high when programmed with JTAG

Hi,

 

Looks like the device is getting programmed but the LED is not glowing as expected. is the expected functionality showing up on the board?

 

Do you have a PULLUP resistor  on the DONE pin? or have you enabled the "drive done" in the bitgen settings? Please check that.

 

Thanks,
Anirudh

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Community Manager
Community Manager
13,484 Views
Registered: ‎07-23-2012

Re: Virtex-5 "Done" signal is not go high when programmed with JTAG

Hi Penn,

Thanks for the update.

If you are able to configure the device using one bit file and was able to see done pin to be working as expected, then we need not suspect the hardware.

Can you please read the status register of the device after the configuration with the MIG bit file?

I suspect that the MIG bit file might have got corrupt.

Regards,
Krishna
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Xilinx Employee
Xilinx Employee
13,478 Views
Registered: ‎07-31-2012

Re: Virtex-5 "Done" signal is not go high when programmed with JTAG

Hi,

 

Can you also send the .bgn file for both the bitfiles? Want to make sure they have similar settings...with respect to drive done and others settings.

Thanks,
Anirudh

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Observer penn
Observer
13,472 Views
Registered: ‎04-02-2014

Re: Virtex-5 "Done" signal is not go high when programmed with JTAG

Hi Krishna,

 

The status register of the device after the configuration with the MIG bit file as follow:

 

'1': Reading status register contents...
CRC error                                                                  :         0
Decryptor security set                                                     :         0
DCM locked                                                                 :         1
DCI matched                                                                :         1
End of startup signal from Startup block                                   :         0
status of GTS_CFG_B                                                        :         0
status of GWE                                                              :         0
status of GHIGH                                                            :         0
value of MODE pin M0                                                       :         1
value of MODE pin M1                                                       :         0
Value of MODE pin M2                                                       :         0
Internal signal indicates when housecleaning is completed                  :         1
Value driver in from INIT pad                                              :         1
Internal signal indicates that chip is configured                          :         0
Value of DONE pin                                                          :         0
Indicates when ID value written does not match chip ID                     :         0
Decryptor error Signal                                                     :         0
System Monitor Over-Temperature Alarm                                      :         0
startup_state[18] CFG startup state machine                                :         0
startup_state[19] CFG startup state machine                                :         0
startup_state[20] CFG startup state machine                                :         0
E-fuse program voltage available                                           :         0
SPI Flash Type[22] Select                                                  :         1
SPI Flash Type[23] Select                                                  :         1
SPI Flash Type[24] Select                                                  :         1
CFG bus width auto detection result                                        :         0
CFG bus width auto detection result                                        :         0
Reserved                                                                   :         0
BPI address wrap around error                                              :         0
IPROG pulsed                                                               :         0
read back crc error                                                        :         0
Indicates that efuse logic is busy                                         :         0

 

 

 


According to the result of my testing,the only possible considersation is the MIG .bit file as you say.

 

Regards,

 

Penn

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Observer penn
Observer
13,140 Views
Registered: ‎04-02-2014

Re: Virtex-5 "Done" signal is not go high when programmed with JTAG

inHi,

 

Thanks a lot.

 

You can find my schematic in my another topic:

http://forums.xilinx.com/t5/Design-Tools-Others/Virtex-5-Programming-failed-with-SPI/td-p/478648

 

The both .bgn files in attachments,  the cpld.bit can be programmed succeeded,and the Done goes high.But the ddr2sdram.bit file can't.

 

Best Regards.

 

Penn

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Xilinx Employee
Xilinx Employee
13,136 Views
Registered: ‎07-31-2012

Re: Virtex-5 "Done" signal is not go high when programmed with JTAG

Hi,

 

The only difference i found in the bgn files is the Match cycle. For the ddr2sdram design it is given as 2 and for the cpld it is given as NoWait. I am not sure if this is a problem but just try to change it to No wait and check. Also let me know if there were any warning during generation of bitfile for the MIG design.

 

However can you clarify one thing here. Check the below and let me know if it is correct.

1) JTAG programming is working only for simple bit file not for the  MIG design

2) SPI programming is failing for both?

 

 

 

Thanks,
Anirudh

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Observer penn
Observer
13,135 Views
Registered: ‎04-02-2014

Re: Virtex-5 "Done" signal is not go high when programmed with JTAG

Hi,

 

No warning during generation of bitfile for the MIG design. I will show it for you.

 

And could you tell me how to change the Match cycle?I am so sorry I can not find it.

 

1) JTAG programming is working only for simple bit file not for the  MIG design

Yes.

2) SPI programming is failing for both?

Yes.you are right.

 

Thanks.

Penn

warning.png

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Xilinx Employee
Xilinx Employee
13,133 Views
Registered: ‎07-31-2012

Re: Virtex-5 "Done" signal is not go high when programmed with JTAG

Hi,

 

It is in the generate programming file properties. Try to regenerate the full design from synthesis to implementation and then generate the bitstream with these options. 

 

MATCH.PNG

Thanks,
Anirudh

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Xilinx Employee
Xilinx Employee
13,128 Views
Registered: ‎07-31-2012

Re: Virtex-5 "Done" signal is not go high when programmed with JTAG

Hi Penn,

 

Also i checked the schematic and found that you have a 270 ohm pullup on the DONE pin externally, which i think is not sufficiente enought. The recommendation from the configuration user guide for V-5 is to have a 330 ohm pullup resistor. However to take care of that, you can give "Drive Done" as Pullup in the same "Generate programming file" properties.

Thanks,
Anirudh

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Observer penn
Observer
13,121 Views
Registered: ‎04-02-2014

Re: Virtex-5 "Done" signal is not go high when programmed with JTAG

Hi,

 

Thank you for patient reply.

 

First, I do not consider that the hardware has a terrible mistake.(So sorry......). and for fear of some unknow state of the board,i change the value of PULL-UP resistance 270 into 330.But the result as before.

 

Besides,I change the Startup Options in Process Properties,the Done does not go high as uausl.

 

Regards.

Penn 

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Community Manager
Community Manager
13,116 Views
Registered: ‎07-23-2012

Re: Virtex-5 "Done" signal is not go high when programmed with JTAG


@penn wrote:

Hi Krishna,

 

The status register of the device after the configuration with the MIG bit file as follow:

 

'1': Reading status register contents...
CRC error                                                                  :         0
Decryptor security set                                                     :         0
DCM locked                                                                 :         1
DCI matched                                                                :         1
End of startup signal from Startup block                                   :         0
status of GTS_CFG_B                                                        :         0
status of GWE                                                              :         0
status of GHIGH                                                            :         0
value of MODE pin M0                                                       :         1
value of MODE pin M1                                                       :         0
Value of MODE pin M2                                                       :         0
Internal signal indicates when housecleaning is completed                  :         1
Value driver in from INIT pad                                              :         1
Internal signal indicates that chip is configured                          :         0
Value of DONE pin                                                          :         0
Indicates when ID value written does not match chip ID                     :         0
Decryptor error Signal                                                     :         0
System Monitor Over-Temperature Alarm                                      :         0
startup_state[18] CFG startup state machine                                :         0
startup_state[19] CFG startup state machine                                :         0
startup_state[20] CFG startup state machine                                :         0
E-fuse program voltage available                                           :         0
SPI Flash Type[22] Select                                                  :         1
SPI Flash Type[23] Select                                                  :         1
SPI Flash Type[24] Select                                                  :         1
CFG bus width auto detection result                                        :         0
CFG bus width auto detection result                                        :         0
Reserved                                                                   :         0
BPI address wrap around error                                              :         0
IPROG pulsed                                                               :         0
read back crc error                                                        :         0
Indicates that efuse logic is busy                                         :         0

 

 

 


According to the result of my testing,the only possible considersation is the MIG .bit file as you say.

 

Regards,

 

Penn



Hi Penn,

 

Is the above status register contents read while configuring the fpga through flash? If yes, please share the contents while configuring in JTAG mode.

 

From the above status register, I could see that the data transmission to the fpga hasn't started.

 

Regards,

Krishna 

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Observer penn
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Registered: ‎04-02-2014

Re: Virtex-5 "Done" signal is not go high when programmed with JTAG

Hi Krishna,

 

I am so sorry that I shared the wrong device status with you.

 

This Device Status is the correct,(JTAG mode)

 

'1': Reading status register contents...
CRC error                                                                  :         0
Decryptor security set                                                     :         0
DCM locked                                                                 :         1
DCI matched                                                                :         1
End of startup signal from Startup block                                   :         0
status of GTS_CFG_B                                                        :         0
status of GWE                                                              :         0
status of GHIGH                                                            :         0
value of MODE pin M0                                                       :         1
value of MODE pin M1                                                       :         0
Value of MODE pin M2                                                       :         1
Internal signal indicates when housecleaning is completed                  :         1
Value driver in from INIT pad                                              :         1
Internal signal indicates that chip is configured                          :         0
Value of DONE pin                                                          :         0
Indicates when ID value written does not match chip ID                     :         0
Decryptor error Signal                                                     :         0
System Monitor Over-Temperature Alarm                                      :         0
startup_state[18] CFG startup state machine                                :         0
startup_state[19] CFG startup state machine                                :         0
startup_state[20] CFG startup state machine                                :         0
E-fuse program voltage available                                           :         0
SPI Flash Type[22] Select                                                  :         1
SPI Flash Type[23] Select                                                  :         1
SPI Flash Type[24] Select                                                  :         1
CFG bus width auto detection result                                        :         0
CFG bus width auto detection result                                        :         0
Reserved                                                                   :         0
BPI address wrap around error                                              :         0
IPROG pulsed                                                               :         0
read back crc error                                                        :         0
Indicates that efuse logic is busy                                         :         0

 

Regards.

Penn

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Observer penn
Observer
13,108 Views
Registered: ‎04-02-2014

Re: Virtex-5 "Done" signal is not go high when programmed with JTAG

As you analysed,the data transmission to the fpga hasn't started, Could you give me some suggestion to correct it?

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Community Manager
Community Manager
13,099 Views
Registered: ‎07-23-2012

Re: Virtex-5 "Done" signal is not go high when programmed with JTAG

Hi Penn,

The .bit/.mcs file will have a sync word. The data after the sync word would the valid configuration data.

The data transmission starts to the fpga after the detection of the syncword.

Usually in JTAG mode, we expect the data transmission to happen unless there are obvious errors like- deviceid mismatch or poor SI of JTAG circuitry etc or if the bit file doesn't have a sync word (this is not a possibility if the tool has generated it).

Regards,
Krishna
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Observer penn
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Registered: ‎04-02-2014

Re: Virtex-5 "Done" signal is not go high when programmed with JTAG

Hi Krishna,

 

You give me more detail explanation and I make sense about the .bit/.mcs file, according the device status,maybe the sync word is in some wrong status?

 

Generally,three reasons may cause this error:device id mismatch,poor SI and the last impossible situation.Now I will exlude it one by one.Because I had programmed the device  before, the second situation is not the reason. So the most probable reason is devicd id...

 

Aften I check the information of my project including the devide,package,speed and so on when I created the project, I find I am back to  the starting point...Aha...

 

Although the problem does not be solved,I may give you real gratitude.

 

Regards,

Penn

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Observer penn
Observer
9,619 Views
Registered: ‎04-02-2014

Re: Virtex-5 "Done" signal is not go high when programmed with JTAG

Hi Krishna,

 

I suppose I have found the reason why the Done signal does not go high.

 

In image of the VCC(3.3V image1),On the moment of the device was programmed,the VCC drop up to about 1.5V.That may lead to the FPGA collapse.

 

But when programmig the others .bit file, this status can not appear.

 

image.png

 

 

Regards,

 

Penn