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Scholar dwisehart
Scholar
10,961 Views
Registered: ‎06-23-2013

Vivado 2013.3 power calcs for LVDS on Kintex-7

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I have 45 lanes of TX and RX LVDS--180 pins in all--but when I do a power calculation it shows only 1 mA of static current and 7 mA of dynamic current being drawn from the 2.5 supply.  

 

Since LVDS pulls 3.5 ma of current per TX lane, the static current should be at least 45 x 3.5 mA = 157.5 mA.  Why is the power calculation so far off?

 

In the xdc file I have:

set_property IOSTANDARD LVDS_25 [get_ports C_RX?*]
set_property IOSTANDARD LVDS_25 [get_ports C_TX?*]
set_property IOSTANDARD LVDS_25 [get_ports D_RX?*]
set_property IOSTANDARD LVDS_25 [get_ports D_TX?*]

 

The IO Planner shows the expected values.  For instance:

C_TXP (18) Output C_TXN     14 LVDS_25 2.50
C_TXP[8] Output C_TXN[8] V25 false 14 LVDS_25 2.50
C_TXP[7] Output C_TXN[7] V29 false 14 LVDS_25 2.50
C_TXP[6] Output C_TXN[6] V27 false 14 LVDS_25 2.50
C_TXP[5] Output C_TXN[5] W24 false 14 LVDS_25 2.50
C_TXP[4] Output C_TXN[4] W26 false 14 LVDS_25 2.50
C_TXP[3] Output C_TXN[3] Y26 false 14 LVDS_25 2.50
C_TXP[2] Output C_TXN[2] AA28 false 14 LVDS_25 2.50
C_TXP[1] Output C_TXN[1] Y28 false 14 LVDS_25 2.50
C_TXP[0] Output C_TXN[0] AB30 false 14 LVDS_25 2.50

 

And I just read the inputs and write them to the outputs so everything is active:

////////////////////////////////////////
wire [8:0] wC_RX;
reg [8:0] rC_TX;

IBUFDS mC_RX [8:0]
(
.I ( C_RXP ),
.IB ( C_RXN ),

.O ( wC_RX )
);

 

OBUFDS mC_TX [8:0]
(
.I ( rC_TX ),

.O ( C_TXP ),
.OB ( C_TXN )
);

 

////////////////////////////////////////
integer i1;

always @( posedge iClk )
for( i1=0; i1<=35; i1=i1+1 )
if( iReset )
rD_TX[i1] <= 1'b0;
else
rD_TX[i1] <= wD_RX[i1];

 

always @( posedge iClk )
for( i1=0; i1<=8; i1=i1+1 )
if( iReset )
rC_TX[i1] <= 1'b0;
else
rC_TX[i1] <= wC_RX[i1];

 

Even the settings the power tool tells me it used for these pins look about right:

Utilization Name I/O Type I/O Standard Input Pins Output Pins Bidir Pins IO LOGIC SERDES IO DELAY IBUF LOW PWR Input Term Clock Name Clock (MHz) Signal Rate (Mtr/s) Data Rate Output Enable (%) Term Disable (%) IBUF Disable (%) Output Load (pF) Vccint (W) Vccaux (W) Vccaux_io (W) Vcco On-chip  (W) External Termination Vcco Off-chip (W)
0.11 DG_Main                                              
0.08 D_RXP HR LVDS_25 36 0 0 No Off Yes NONE N/A 0.00 40.28 Async 0.00 0.00 0.00 0.00 0.01 0.06 0.00 0.00 NONE 0.00
0.02 C_RXP HR LVDS_25 9 0 0 No Off Yes NONE N/A 0.00 40.28 Async 0.00 0.00 0.00 0.00 0.00 0.02 0.00 0.00 NONE 0.00
0.01 D_TXP HR LVDS_25 0 36 0 No Off No NONE mClk/inst/o312Clk 312.50 39.06 SDR 100.00 0.00 0.00 0.00 0.00 0.00 0.00 0.01 FD_100 0.00
0.00 C_TXP HR LVDS_25 0 9 0 No Off No NONE mClk/inst/o312Clk 312.50 39.06 SDR 100.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 FD_100

0.00

 

 

 

So why is the calculated power too low?

 

Thanks,

Daniel

 

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1 Solution

Accepted Solutions
Scholar dwisehart
Scholar
16,585 Views
Registered: ‎06-23-2013

Re: Vivado 2013.3 power calcs for LVDS on Kintex-7

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The question I had about LVDS power calcs was a bug on versions through 2014.1 (and maybe 2014.2) but has been fixed with version 2014.3.1.

 

Many thanks,

Daniel

 

PS. In case anyone else is interested, it was an Avnet FAE that was finally able to help me.  I had to keep asking Xilinx and Avnet people for assistance.  It was finally a Xilinx person here on the Forums who helped close the loop.

 

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5 Replies
Scholar dwisehart
Scholar
10,950 Views
Registered: ‎06-23-2013

Re: Vivado 2013.3 power calcs for LVDS on Kintex-7

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I wonder if I need to set the capacitance of the outputs or if other loads need to be triggered in the power calcs.  It is obvious that the GTX ports are doing this because they calculate power draw quite well.

 

Thanks for your suggestions,

Daniel

 

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Scholar dwisehart
Scholar
10,912 Views
Registered: ‎06-23-2013

Re: Vivado 2013.3 power calcs for LVDS on Kintex-7

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I am not getting any help in resolving this.  Is there someone at Xilinx I can contact directly or who might be convinced to look at my question?  Who worked on the power calculation software?

 

Thanks,

Daniel

 

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Xilinx Employee
Xilinx Employee
10,864 Views
Registered: ‎08-01-2012

Re: Vivado 2013.3 power calcs for LVDS on Kintex-7

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In LVDS part of source power returns back.

 

 

 

The XPE/XPA power consumption data is based upon the characterization data

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Scholar dwisehart
Scholar
10,858 Views
Registered: ‎06-23-2013

Re: Vivado 2013.3 power calcs for LVDS on Kintex-7

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Thanks for the reply, Kodali.  I do appreciate it.

 

LVDS, by definition, requires 3.5 mA of static current driven from each pair of outputs.  Yes, the LVDS pair of inputs is receiving 3.5 mA of static current from the other IC: another Virtex-7 FPGA in this case.  But the transmit static and dynamic power must still be sourced by the FPGA power supplies, regardless of how much power is being sourced by the other IC in the communications.

 

In my little example, I have 45 LVDS TX/RX pairs: 180 traces in total.  At a minimum, the static current required is 45 x 3.5 mA = 157.5 mA per FPGA, and that assumes no leakage current through the 180 protection diodes on the 90 transmit traces.  The power estimation tool in Vivado is showing 1 mA of static current.  Either I have not set something up correctly, or the tool is broken and needs to be fixed.

 

I am running my LVDS pairs at 312.5 MHz, so each pair will not drive a lot of current, but 7 mA divided by 45 pairs is only 156 micro-amps of dynamic current each.  That sounds too small.  What sort of rise time are you expecting and how much total capacitance are you anticipating that the transmitter will be driving?

 

So do I have something set up wrong for the power calculations, or is there some investigation that is needed into the power calculations being done for LVDS?

 

Many thanks for your attention to this matter,

Daniel

 

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Scholar dwisehart
Scholar
16,586 Views
Registered: ‎06-23-2013

Re: Vivado 2013.3 power calcs for LVDS on Kintex-7

Jump to solution

The question I had about LVDS power calcs was a bug on versions through 2014.1 (and maybe 2014.2) but has been fixed with version 2014.3.1.

 

Many thanks,

Daniel

 

PS. In case anyone else is interested, it was an Avnet FAE that was finally able to help me.  I had to keep asking Xilinx and Avnet people for assistance.  It was finally a Xilinx person here on the Forums who helped close the loop.

 

View solution in original post

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