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Visitor
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Registered: ‎06-10-2014

Vivado 2014.1 ILA transeiver wizard example design

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I tried to implement the example design for the Virtex-7 Transeivers Wizard and inserted ILA into my design. I am able to compile and implement, however, when debugging, my outputs are not correct. 

For example, the output for probe 1 is supposed to be gt0_error_count_i. Also if there are more transeivers added beyond gt0, they all just give a n_9_gt0_framecheck type of output.

 

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Visitor
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Registered: ‎06-10-2014

Fixed it.

 

You have to 1. make sure to select "none" on Flatten Hiearchy in the Synthesis settings

 

2. make sure to mark_debug all signals youre probing before the main line of code.

go to pg. 19 here for how to:

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug908-vivado-programming-debugging.pdf

 

That should do it, I think!

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Visitor
Visitor
16,971 Views
Registered: ‎06-10-2014

Fixed it.

 

You have to 1. make sure to select "none" on Flatten Hiearchy in the Synthesis settings

 

2. make sure to mark_debug all signals youre probing before the main line of code.

go to pg. 19 here for how to:

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug908-vivado-programming-debugging.pdf

 

That should do it, I think!

View solution in original post

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