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xromka
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Visitor
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Registered: ‎07-26-2017

Vivado 2017.2 (and 2017.3) resets FPGA if execute open_hw_target command

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Hi

Configuration: Vivado 2017.2, Windows7-64bit, Xilinx USB II JTAG programming cable.
FPGA board with the xcku085-flvb1760 chip. If this FPGA is programmed and I connect to FPGA thru JTAG programming cable, by executing the command in Flow Navigator:   "PROGRAM_AND_DEBUG -> Open_Target -> Auto_Connect "  this FPGA is resetting ( goes to unprogrammed state). This causes problems when debugging eg. PCIe.
Executing connecting command step by step I found the resetting FPGA is happening if execute  open_hw_target command.
Reset occurs only when first connected - the subsequent work of JTAG has no problems.

Versions of Vivado (2016.4, 2017.1) on the same computer configuration and board doesn't reset FPGA if execute the open_hw_target command. I checked two combinations of the source for loading FPGA  (onboard parallel flash and JATG)  and various combinations of power cycle and connection JTAG cable,  in any variants behavior the same. I tested this solution "set_param labtools.auto_update_hardware 0" but no any effect.

In addition, when checking a connection from Vivado 2017.1 I see that it uses hw_server 2017.2 so it seems to me that it's not about the hw_server settings.

The new version of Vivado 2017.3 is the same behavior. Resetting the FPGA after running open_hw_target.

It possible fix this?

Best regards, Roman.

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xromka
Visitor
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Registered: ‎07-26-2017

Hi,

 

In the Vivado 2017.4 the solution it worked.
Thanks!

 

Good luck,
   Roman.

 

 

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6 Replies
iguo
Xilinx Employee
Xilinx Employee
2,754 Views
Registered: ‎08-10-2008
Hi, Roman,

Seems a JPROG was issued. Check the Vivado log, is there a boot_hw_device? If there is, move it.
Otherwise, open_hw_target may trigger silently a JPROG; this is useful when you do a remote programming but not in your case.

Thanks,
Ivy
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ingmarvanklink
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Registered: ‎11-03-2017

Hi,

 

Lots of our customers are reporting this issue to us. They get a board which has a pre-programmed flash device, they powerup the PCIe system and the FPGA configures from the flash device. They also connect to JTAG, and when they scan the chain with Vivado 2017.2 or higher, the device says "unprogrammed", this is a bad first impression of our products.

I have opened a ticket about this as well: SR#10414726. Are there plans within Xilinx to solve this issue? 

 

Thanks,

Ingmar 

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klyndt
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2,170 Views
Registered: ‎09-08-2015

Any update to this problem?  I have the same issue.  My init and prog lines run over to another JTAG device.  That device appears to get reset too.  I'm thinking this is some sort of JTAG command to reset the devices in the JTAG chain.  We are using 2017.4 and 2018.1. 

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hj
Moderator
Moderator
2,160 Views
Registered: ‎06-05-2013

Hi,

 

Here the link to AR which has patch https://www.xilinx.com/support/answers/70942.html 

 

If AR link doesn't work then use the patch which is attached here. Please follow the steps which are provided in readme file. 

 

Thanks

Harshit

 

 

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For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
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klyndt
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2,149 Views
Registered: ‎09-08-2015

This solved it.  I used the files from the AR.  I didn't try the attached files.  Thank you for the quick reply.

xromka
Visitor
Visitor
2,584 Views
Registered: ‎07-26-2017

Hi,

 

In the Vivado 2017.4 the solution it worked.
Thanks!

 

Good luck,
   Roman.

 

 

View solution in original post

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