05-16-2018 08:27 AM
I am attempting to view signals in a simple design using the Clocking Wizard and SerialIO IPs, but after selecting which nets to debug and clicking "Generate Bitstream", Vivado has been running route_design for well over an hour. Are there any ways to speed up this process?
05-17-2018 10:36 AM
If you generate the bitstream without the ILA does it goes much faster?
How many ILAs and how many probes do you have in the design? If you try with one ILA and only one probe (just for testing purposes), does it get faster or still very slow?