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Adventurer
Adventurer
494 Views
Registered: ‎08-15-2018

Vivado Core Dump - IBERT Example Design Greyed Out, fixed by reset?

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When I generate the IBERT from the wizard in 2018.3, I generate output products. But when I right click on the .xci, "Open IP Example Design" is greyed out.

I have to 'Reset Output Products', and then the Example Design isn't greyed out. What is going on here?

 

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Xilinx Employee
Xilinx Employee
459 Views
Registered: ‎10-19-2011

Re: IBERT Example Design Greyed Out, fixed by reset?

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Hi @bitstreamer ,

can it be that you did not wait until the output products were fully created? There usually is a synthesis run working in the background and you would get the menu item only available when this run finished. You should see that process running at the top right of the GUI.

On the other hand, for creating the example design you do not need the output products in the initial project. They will be recreated in the example design anyway.

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Xilinx Employee
Xilinx Employee
460 Views
Registered: ‎10-19-2011

Re: IBERT Example Design Greyed Out, fixed by reset?

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Hi @bitstreamer ,

can it be that you did not wait until the output products were fully created? There usually is a synthesis run working in the background and you would get the menu item only available when this run finished. You should see that process running at the top right of the GUI.

On the other hand, for creating the example design you do not need the output products in the initial project. They will be recreated in the example design anyway.

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Adventurer
Adventurer
444 Views
Registered: ‎08-15-2018

Re: IBERT Example Design Greyed Out, fixed by reset?

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Yes - that's what I thought - it says 'Ready', not the usual indicator of synthesis or something running.

Upon further inspection - I believe it's 'silently' failing with a core dump in a background process. Any suggestions???

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Adventurer
Adventurer
436 Views
Registered: ‎08-15-2018

Re: IBERT Example Design Greyed Out, fixed by reset?

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Narrowed it down to this

/home/tools/Vivado/2018.3/bin/vivado &
[@localhost ~]$ terminate called after throwing an instance of 'HEXAlgException'
what(): ERROR: [Common 17-70] Application Exception: File not found: /mnt/hgfs/dir/prj.runs/ibert_ultrascale_gty_0_synth_1/runme.sh

/home/tools/Vivado/2018.3/bin/loader: line 213: 28534 Aborted (core dumped) "$RDI_PROG" "$@"
[@localhost ~]$ ls /mnt/hgfs/dir/prj.runs/ibert_ultrascale_gty_0_synth_1/runme.  <tab>
runme.bat runme.sh

It's there, but vivado doesn't see it and core dumps.

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Xilinx Employee
Xilinx Employee
408 Views
Registered: ‎10-19-2011

Re: IBERT Example Design Greyed Out, fixed by reset?

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Hi @bitstreamer ,

that looks like an environment issue and not IBERT specifically. This is a bit out of my knowledge. Maybe someone else can help you further here.

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