Vivado Error :[Labtools 27-1474] with ILA

[brittledia]

Hi~
I use Vivado 2003.1 version.
When I had not add ILA, my project file is good work. And I had verify my bit file by download to FPGA.
When I add ILA, Synthesis and Implementation are finished successfully.
But, Error occured if I download my bit file to FPGA.
Error message is like this.

I just add 1 ILA. My setting is like this.

How can I solve this problum?

[brittledia]

My error message is 

"The probes file associated with this device contains information about a debug core that does not match the information extracted from the design that is currently programmed into this device."

My sampling clock name is "clk_ref". My probe signal is frequency divider by 2 of clk_ref.

[pratham]

Hello,

1) Make sure that the design that is programmed into the device matches the probes file (.ltx) that is associated with the device. Re-program and refresh the device, if needed.
2) Re-generate the bitstream file (using the write_bitstream Tcl command) and re-generate the probes file (using the write_debug_probes Tcl command), then re-program and refresh the device.

[brittledia]

I have no idea for this message.

I use Vivado 2013.3 with same HDL code. And error message is 

"Mismatch between the design programmed into the device XC7VX330T_0 and probes file D:/test/EErase/EErase/EErase.runs/impl_1/debug_nets.ltx.

The device design has 0 ILA core(s) and 0 VIO core(s). The probes file has 1 ILA core(s) and 0 VIO core(s)."

I have question. What is device design and how can I fix them?

[achutha]

Hi,

I would recommend to re-create the project in 2013.3 and assign the pins to debug and generate the debug.ltx.

Regards,
Achutha

[pratham]

Hello,

That Error message says that design doesn't have a ILA or VIO core but whereas .ltx file has a 1 ILA & 0 VIO core.

Can you just open .ltx and check it if the signals which you wanted to debug are present over there and at the same time open the implemented design and slest the debug mode and check for the debug signals and ila core.

If you see the difference in the .ltx and implemented design then it should be corrected.

Regards,
Pratham

[pratham]

Hello,

Are you sure about you dumped the same bit file the one which tool generated for this project.

That Error message says that design doesn't have a ILA or VIO core but whereas .ltx file has a 1 ILA & 0 VIO core.

Can you just open .ltx and check it if the signals which you wanted to debug are present over there and at the same time open the implemented design and slest the debug mode and check for the debug signals and ila core.

If you see the difference in the .ltx and implemented design then it should be corrected.

Regards,
Pratham

[brittledia]

Thank you for your reply.

I checked my ltx file. I think that ltx file has no problum.

My ltx file is this.

<?xml version="1.0" encoding="UTF-8"?>
<probeData version="1" minor="1">
<probeset name="EDA_PROBESET" active="true">
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="COMPARE_VALUE.0" value="eq1&apos;bX"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="0"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="n_0_double_clk_reg"/>
</nets>
</probe>
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
<probeOptions Id="DebugProbeParams">
<Option Id="COMPARE_VALUE.0" value="eq1&apos;bX"/>
<Option Id="CORE_LOCATION" value="1:0"/>
<Option Id="HW_ILA" value="u_ila_0"/>
<Option Id="PROBE_PORT" value="1"/>
<Option Id="PROBE_PORT_BITS" value="0"/>
<Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
</probeOptions>
<nets>
<net name="n_0_sw_IBUF[0]_inst"/>
</nets>
</probe>
</probeset>
</probeData>

But, I have some difference with your attected picture.

My project has not ila icon. 

After synthesis, I implement debug core before implement my logic.

[vemulad]

Hi,

Open Implemented design and run the command

write_bitstream test.bit

This creates a new .bit file. Now open hardware session and program the device using this new .bit file and .ltx file. Let us know if this helps.

Thanks,

Deepika.

[john1483]

Hi

I am also facing the same issue, I am using Vivado 2013.3 and Artix device,  when I open the implemented design, I see that dbg_hub and ILA_0 are placed and connected also, but if I open the hardware manager and open target and program the bit file, it says mismatch  and probes file has one debug_core but deesign has 0(zero) cores.

Please let me know ASAP if any one has found solution for this

[john1483]

Hello Deepika,

I have not heard  anything from any one, anyone fron xlinx or some one else can help me on this, this has become very problamatic debugging in Vivado, infact this vivado analyzer is making debug painful.

  In the implemented design it shows the debug_hub and ILa and probe file also has the core, but when I open target and prog bit file it cribs saying design has no debug core but probe file has.

No appropriate documentaion is also available on issues withh Viavdo analyzer this is delaying the projects like anything....

[pratham]

Hello,

Sorry for the delayed response.

Have you followed all the suggestions earlier posted on this thread? the error message says design bit file doesn't have any debug core but LTX file has the debug core.
please make sure your using the bit file of the same design which has core in it.

If this suggestion also doesn't help i would like to take a look at the design. please let me know if you can share the design which can reproduce this problem

[ericdormer1962]

I will add my name to the list of people stumped by the problem of the bitfile not matching the probes file.   I have read everything I can find on this forum about this and the standard advice seems to be "ensure the bitfile and probes file refer to the same design".   They do. 

Details: 

In particular, I am using a 2013.3, Vivado IPI flow (of a microblaze design) with a hand coded verilog top level.

While the microblaze block diagram is open, I export the system information to the SDK.   Then I proceed with

synthesis which works fine. Then I select a set of signals to attach to ILA cores, using the "setup debug" feature.    

Then I implement design, and all goes well.   Then I generate the bitfile.   Then I export the bitfile and system 

to the SDK.  Then I open it in the SDK and which usually recompiles the library files to align with the system

information. Then I download to FPGA, while specifying the impl_1/toplevel.bit  and impl_1/toplevel.bd.bmm files

as the raw bitfile (and memory information file) allowing the ELF executable to be inserted to generate download.

bitfile.  Then I go back to the Xilinx Vivado tool, and open the Hardware Manager.  

I enter the Hardware Device Properties panel, and I select the download.bit file from the SDK area (where it was put

after the ELF file was inserted into the toplevel.bit bitfile. )  For the probes file I select the debug_nets.ltx file  from the

impl_1 directory itself. 

Back in the hardware manager panel, I select the localhost and Dilligent interface, and then right click on the

device (XC7VX485T_0), and select the menu item, "program device".  I reprogram the device, and then the

error message pops up saying the download.bit file does not match the debug_nets.ltx file.   

"ERROR: [Labtools 27-1974] Mismatch between the design programmed into the device XC7VX485T_0

and the probes file C:/Work/.../althea.runs/impl_1/debug_nets.ltx  . The device design has 0 ILA core(s)

and 0 VIO core(s). The probes file has 1 ILA core(s) and 0 VIO core(s)."

I have tried this process dozens of ways, having chased this for two full days.  I am frustrated. 

This problem occurred once before about a month ago, and at that time I wasted a couple of days trying to figure out

what was going on.  Somehow, the problem cleared up by itself, no idea why.   This time, the problem persists. 

I have confirmed the ILA cores are in the implemented design.  I have reviewed the debug_nets.ltx file and it looks 

fine also, with the correct signal names.  

The "mismatch" problem only reveals itself when you actually try to program the device and use the probes file,

and then it announces the debug_nets.ltx does not match the download.bit file. 

(By the way, I also tried downloading just the toplevel.bit file, with the debug_nets.ltx file (ie with no ELF 

code inserted), and I get the same error. 

Any idea what causes this?

Frustrated user!

-- Eric 

[yxcvbn1]

Hi all,

I want to let you know that there are more users running into similar issues:

http://forums.xilinx.com/t5/Design-Entry/Hardware-Manager-error-relative-ila-ip-core-vivado-13-4/td-p/396319

I have opened a WebCase for this topic, hope that forces to get an idea what the root cause of the issue is: wrong usage of ILA in the IPI flow or something wrong in the Vivado tool.

If you want you can send me your email contact info (click on my logo and use 'send private message'). I will try to set you on the email thread of the WebCase.

Hope we got this issue resolved soon!

Ric.

[kunalarya]

In case anyone stumbles on this forum post, I had the same exact problem (using Vivado 2014.1 with a Zedboard). For whatever reason, I was able to get this to work if I connected to the logic analyzer via SDK. UG940 describes how to do this in the section "Lab 2: Using SDK and the Vivado Logic Analyzer." This only helps if you're using an embedded system. It may be helpful to someone here.

[numbat]

kunalarya,

Your fix got my embedded system working with 2013.4.

Thanks!