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Explorer
Explorer
9,174 Views
Registered: ‎06-13-2013

Vivado ILA problems

Xilinx,

 

I am having troubles getting the ILA to work in my project.

 

I went to training and took the Xilinx course  Zynq All Programmable Soc System Architecture.  Lab 4  was a lab on Debugging on the Zynq all programmable SoC.   I redid the lab and I can get the project to work with the ILA.  I go ahead and do the same steps but add ILA to just my project.   When I get to the Hardware Manager and Click on Run Trigger Immediate the waveform file does not pop up.  The button to open the waveform is also greyed out.  I am not sure what I am doing that is wrong.

 

ILA.png

 

 

This is the Block design.

 

ila2.png

 

Any help would be appreciated.

 

If I can't get it to work by the end of the day I am basically never going to use the ILA.  I will just use my external Logic analzyer since it is more powerful and not buggy but it be nice to be able use this sometimes.

 

Thanks

 

C

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7 Replies
Xilinx Employee
Xilinx Employee
9,166 Views
Registered: ‎02-06-2013

Re: Vivado ILA problems

Hi

 

Add the probes from the debug probes window to the ILA window and check.

Regards,

Satish

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Explorer
Explorer
9,154 Views
Registered: ‎06-13-2013

Re: Vivado ILA problems

That window is the trigger window.  You shouldn't need any triggers if you click the Trigger immediate.  

 

Still "greyed out" ila3.png

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Xilinx Employee
Xilinx Employee
9,132 Views
Registered: ‎09-20-2012

Re: Vivado ILA problems

Hi,

Can you try reducing the jtag cable frequency and see if it helps?

Thanks,
Deepika.
Thanks,
Deepika.
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Explorer
Explorer
9,120 Views
Registered: ‎06-13-2013

Re: Vivado ILA problems

I reduced Jtag to 1 MHz from 15 MHz and it appears to be working.  I still have to test when my software resource is in the office.

 

But is there a reason why the 15 MHz jtag frequency doesn't work with my design and works with the Tutorial design with the same hardware?   

 

The default was set at 15 MHz and I just left it as is.  

 

Why does this happen?

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Xilinx Employee
Xilinx Employee
9,116 Views
Registered: ‎09-20-2012

Re: Vivado ILA problems

Hi,

 

The JTAG cable frequency has to be lesser than ILA clock frequency.

 

Check this thread  http://forums.xilinx.com/t5/Vivado-TCL-Community/Set-trigger-and-get-waveform-by-Vivado/td-p/433848

 

Thanks,

Deepika.

Thanks,
Deepika.
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Explorer
Explorer
9,105 Views
Registered: ‎06-13-2013

Re: Vivado ILA problems

Well in the thread it says that the Jtag Frequency must be lower than the ILA frequency.  In which my original design I had the JTAG at 15 MHz and then when i switched to 1 MHz it worked.

 

My question is "Why does the JTAG frequency have to be lower than the ILA frequency"??

 

 

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2,548 Views
Registered: ‎11-25-2016

Re: Vivado ILA problems

Hi,

 

I am trying to use ILA for in-system debugging. I have followed "Netlist insertion" workflow. I am able to see the waveforms after pressing "Immediate trigger". But, it is not showing any transitions, it is showing constant values only. 

 

I would also like to know why JTAG TCK frequency should be less than ILA clock frequency.

 

Thanks in advance.

 

Jeet

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