I am new to Xilinx and I am working on logic analyzer for my company project. I have one question.
Do I have to recompile the project after setting and resetting triggers condition in Vivado logic analyzer? If yes/no, any document can be pointed here? Many thanks and appreciate it
No, the ILA trigger conditions are generated at run time, so you do not need to recompile the project after changing the triggers.
You will only need to recompile the project if you want to add/remove probes to the ILA, or add other ILAs to the project.
Information about how to use the ILA trigger conditions can be found in the document Vivado Programming and Debugging User Guide - UG908, pg. 179, "Using the ILA Default Dashboard".