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shaileshkumar
Visitor shaileshkumar
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‎11-04-2014 11:29 PM

9,952 Views
Registered: ‎11-04-2014

Vivado chipscope error

refresh_hw_device [lindex [get_hw_devices] 1]
INFO: [Labtools 27-1432] Device xc7z030 (JTAG device index = 1) is programmed with a design that has 1 ILA core(s) in it.
ERROR: [Labtools 27-1972] Mismatch between the design programmed into the device xc7z030 (JTAG device index = 1) and the probes file D:/VHDL/cdma_aiv/ZYNQ_ADC_TRK/zynq/Ade_test_proj.runs/impl_1/debug_nets.ltx.
 The core at location user chain=1 index=0 has different widths for ILA input port 0. Port width in the device core is 0, but port width in the probes file is 10.
Resolution: Make sure the device probes file is up-to-date, then re-program the device.

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vuppala
Xilinx Employee
Xilinx Employee

‎11-05-2014 12:24 AM

9,944 Views
Registered: ‎04-16-2012

Re: Vivado chipscope error

Hello,

This issue generally occurs when .bit and .ltx files do not match.
Make sure you are using correct .ltx file and .bit files.

Thanks,
Vinay
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shaileshkumar
Visitor shaileshkumar
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‎11-05-2014 08:56 PM

9,924 Views
Registered: ‎11-04-2014

Re: Vivado chipscope error

both .bit and .ltx are proper, still getting same error

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vijayak
Xilinx Employee
Xilinx Employee

‎11-07-2014 08:37 AM

9,911 Views
Registered: ‎10-24-2013

Re: Vivado chipscope error

Hi,
Moving to Design tools -others board.
Thanks,Vijay
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shaileshkumar
Visitor shaileshkumar
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‎11-10-2014 02:37 AM

9,823 Views
Registered: ‎11-04-2014

Re: Vivado chipscope error

I checked in artix 7 also. i got same error
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