09-10-2019 08:59 AM
@markcurry: parallel synthesis does not kick in when the design is too small (no compile time gain) or when complex timing constraints are applied to the design. This last condition should be addressed in the coming Vivado release (2019.2).
09-10-2019 09:02 AM
09-10-2019 09:03 AM
Hi @sturmel2007 : it looks like you have misinterpreted the content of https://www.xilinx.com/products/design-tools/vivado/memory.html. This page shows that system memory guidelines are the same for Windows and Linux. For each device, there is a typical memory utilization (average design with average timing constraints complexity), and a peak memory utilization (maximum observed by Xilinx on a large set of designs, due to high utilization, congestion, complex timing constraints, etc...).
09-10-2019 09:15 AM
@sturmel2007: thanks for your faith :)! Unfortunately, this is not something Xilinx spends time on. I'll restate the reasoning behind it:
1) There are too many different systems to benchmark. Xilinx focuses on release to release compile time comparison for a same system & OS, and whenever needed, competitive analysis as well.
2) Windows vs Linux performance differences are not unique to Vivado or any Xilinx tools. General information on this topic should be available on the web. Linux is generally more efficient as it is a leaner OS with fewer extra services/processes burning compute resources (firewall, disk encryption, web browsers, etc...).
I hope this closes this thread. Thanks for sharing your thoughts and findings!
09-11-2019 05:01 AM