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Adventurer
Adventurer
310 Views
Registered: ‎05-18-2018

Vivado not recognizing debug core despite it showing up in schematic

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I am trying to figure out ILA with a ZYNQ 7010 SoC and am having trouble getting Vivado to recognize that my debug cores exist. I am using Vivado 2019.1 and a MicroZed. Despite showing up as synthesized and appearing in the schematic, I get warnings in the bitstream generation phase that no debug cores are present.

My process:

First I created a simple block design with a binary counter. I set up FCLK_CLK0 to 100 MHz (clocking the ILA and VIO cores) and FCLK_CLK3 to 10 MHz (clocking the counter). I used the VIO block because Vivado threw an error saying that I/O was not fabric-accessible.Block_design.png

system_ila_recustomization.png

The design synthesized with no errors. I then used the command implent_debug_core. This process completed without errors.implement_debug_cores.png

I used the Set Up Debug to look at positions 0, 1, 14, and 15 of the counter, selected from the Netlist View, and had to select my clock domain. I picked FCLK_CLK0.ila_core_options.png

 

clock_domain_debug_setup.png

I resynthesized and the dbg_hub core is clearly visible.
netlist_detail_after_resynthesis.png

I then implemented the design with no errors or critical warnings.

Then I generated the bitstream with no errors or critical warnings.

I finally opened the Hardware Manager and got the following:

 

no_debug_cores_banner.pngdebug_core_error_messages.png


"The debug hub core was not detected."

Following Vivado's suggestion to look at UG908, I did not see error "[Labtools 27-3361] The debug hub core was not detected".

I ran the command get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub], which returned 1, if this helps at all.C_USER_SCAN_CHAIN_result.png

I am stuck at this point. Is there or isn't there a debug hub? What is going on?

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Moderator
Moderator
261 Views
Registered: ‎02-09-2017

Re: Vivado not recognizing debug core despite it showing up in schematic

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Hi @joelschad,

 

Since the clock you are using is generated by the PS, you need to first start the PS resources before programming the PL and opening the ILA.

The correct flow would be to generate the bitstream in Vivado, export the hardware to SDK, create a Hello World application to start the PS and program the FPGA from the SDK.

The flow you have to follow is as show in the document Embedded Processor Hardware Design - UG940, Lab 1 (please take a look at Step 3 to make sure you're instantiating the ILA correctly, and then I believe you can skip to Step 6, page 24).

If that still does not work, please let us know.

Thanks,

 

Andre Guerrero

Product Applications Engineer

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4 Replies
Adventurer
Adventurer
306 Views
Registered: ‎05-18-2018

Re: Vivado not recognizing debug core despite it showing up in schematic

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More info... I programmed the part anyway, but to no avail:

 

 

programming_anyway.pngstill_not_detected_after_programming.png

 

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Adventurer
Adventurer
297 Views
Registered: ‎05-18-2018

Re: Vivado not recognizing debug core despite it showing up in schematic

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There is a .xdc file in the project that references the points I wish to debug:

create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 65536 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list design_1_i/processing_system7_0/inst/FCLK_CLK0]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 4 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {design_1_i/c_counter_binary_0_Q[0]} {design_1_i/c_counter_binary_0_Q[1]} {design_1_i/c_counter_binary_0_Q[14]} {design_1_i/c_counter_binary_0_Q[15]}]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]

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Moderator
Moderator
262 Views
Registered: ‎02-09-2017

Re: Vivado not recognizing debug core despite it showing up in schematic

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Hi @joelschad,

 

Since the clock you are using is generated by the PS, you need to first start the PS resources before programming the PL and opening the ILA.

The correct flow would be to generate the bitstream in Vivado, export the hardware to SDK, create a Hello World application to start the PS and program the FPGA from the SDK.

The flow you have to follow is as show in the document Embedded Processor Hardware Design - UG940, Lab 1 (please take a look at Step 3 to make sure you're instantiating the ILA correctly, and then I believe you can skip to Step 6, page 24).

If that still does not work, please let us know.

Thanks,

 

Andre Guerrero

Product Applications Engineer

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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
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Adventurer
Adventurer
113 Views
Registered: ‎05-18-2018

Re: Vivado not recognizing debug core despite it showing up in schematic

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We're not using SDK to develop the PS-side code, but this was an order-of-flow issue, which has been resolved.

Thanks.

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