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Observer guidopc
Observer
7,049 Views
Registered: ‎04-04-2016

Vivado v2015.4 (64-bit) SW Build 1412921: File -> Archive Project

Archiving fails.

tcl window log follows:

archive_project C:/Xilinx/Workspace/GalateaPDEngine_MECTEC20160414.xpr.zip -temp_dir C:/temp -force -include_config_settings
INFO: [Coretcl 2-137] starting archive...
INFO: [Coretcl 2-1499] Saving project copy to temporary location 'C:/temp' for archiving project
INFO: [Coretcl 2-1211] Creating project copy for archival...
INFO: [Coretcl 2-1213] Including run results for 'synth_1'
INFO: [Coretcl 2-1213] Including run results for 'impl_1'
INFO: [Coretcl 2-1212] Importing remotely added design sources and verilog include files (if any)...
INFO: [filemgmt 20-334] All file(s) are already imported in fileset: 'constrs_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'constrs_1'
INFO: [filemgmt 20-334] All file(s) are already imported in fileset: 'sim_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sim_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sources_1'
WARNING: [Coretcl 2-232] Detected issues while importing sources. Closing temporary saved as project...
****** Webtalk v2015.4 (64-bit)
**** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
**** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/temp/PrjAr/_X_/GalateaPDEngine_MECTEC20160414.hw/webtalk/labtool_webtalk.tcl -notrace
webtalk_transmit: Time (s): cpu = 00:00:00 ; elapsed = 00:01:20 . Memory (MB): peak = 49.879 ; gain = 0.043
INFO: [Common 17-206] Exiting Webtalk at Wed Apr 20 09:12:28 2016...
ERROR: [Coretcl 2-230] (archive_project): Received exception while importing sources. Please check for any errors reported in the Tcl Console.

Can anyone help?

Thank you

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4 Replies
Xilinx Employee
Xilinx Employee
6,701 Views
Registered: ‎07-21-2014

Re: Vivado v2015.4 (64-bit) SW Build 1412921: File -> Archive Project

Hi,

Did you try resetting runs (synth and impl) and then archive?
What is the operating system?

-Shreyas

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Xilinx Employee
Xilinx Employee
6,654 Views
Registered: ‎07-21-2014

Re: Vivado v2015.4 (64-bit) SW Build 1412921: File -> Archive Project

Hi @guidopc

Any updates on this?

-Shreyas
----------------------------------------------------------------------------------------------
Try to search answer for your issue in forums or xilinx user guides before you post a new thread.

Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
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Observer guidopc
Observer
6,653 Views
Registered: ‎04-04-2016

Re: Vivado v2015.4 (64-bit) SW Build 1412921: File -> Archive Project

Apologies, I received the reply alert only now.

Windows 7 Pro - 64 bit

I didn't try the proposed solution yet

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Observer rforsyth
Observer
3,005 Views
Registered: ‎03-25-2013

Re: Vivado v2015.4 (64-bit) SW Build 1412921: File -> Archive Project

 

 

I had this problem and found that when I had gone to "add sources" to add a Verilog file. This file was not used by the project so I had no trouble implementing everything. But I found that this particular Verilog file had instantiations, and the sources for those instantiations had not been added to the project - so they showed the red question mark.

 

This is not visible when the source file hierarchy is not expanded, so not at all obvious. Removing the unused source allowed me to archive.

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