04-20-2016 01:23 AM
tcl window log follows:
archive_project C:/Xilinx/Workspace/GalateaPDEngine_MECTEC20160414.xpr.zip -temp_dir C:/temp -force -include_config_settings
INFO: [Coretcl 2-137] starting archive...
INFO: [Coretcl 2-1499] Saving project copy to temporary location 'C:/temp' for archiving project
INFO: [Coretcl 2-1211] Creating project copy for archival...
INFO: [Coretcl 2-1213] Including run results for 'synth_1'
INFO: [Coretcl 2-1213] Including run results for 'impl_1'
INFO: [Coretcl 2-1212] Importing remotely added design sources and verilog include files (if any)...
INFO: [filemgmt 20-334] All file(s) are already imported in fileset: 'constrs_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'constrs_1'
INFO: [filemgmt 20-334] All file(s) are already imported in fileset: 'sim_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sim_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sources_1'
WARNING: [Coretcl 2-232] Detected issues while importing sources. Closing temporary saved as project...
****** Webtalk v2015.4 (64-bit)
**** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
**** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
source C:/temp/PrjAr/_X_/GalateaPDEngine_MECTEC20160414.hw/webtalk/labtool_webtalk.tcl -notrace
webtalk_transmit: Time (s): cpu = 00:00:00 ; elapsed = 00:01:20 . Memory (MB): peak = 49.879 ; gain = 0.043
INFO: [Common 17-206] Exiting Webtalk at Wed Apr 20 09:12:28 2016...
ERROR: [Coretcl 2-230] (archive_project): Received exception while importing sources. Please check for any errors reported in the Tcl Console.
Can anyone help?
04-28-2016 01:48 AM - edited 04-28-2016 01:49 AM
Did you try resetting runs (synth and impl) and then archive?
What is the operating system?
04-29-2016 12:45 AM
04-29-2016 12:48 AM
Apologies, I received the reply alert only now.
Windows 7 Pro - 64 bit
I didn't try the proposed solution yet
04-08-2017 11:57 AM
I had this problem and found that when I had gone to "add sources" to add a Verilog file. This file was not used by the project so I had no trouble implementing everything. But I found that this particular Verilog file had instantiations, and the sources for those instantiations had not been added to the project - so they showed the red question mark.
This is not visible when the source file hierarchy is not expanded, so not at all obvious. Removing the unused source allowed me to archive.