UPGRADE YOUR BROWSER
We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
07-21-2017 01:37 AM
Hi,
I'm using VIVADO 2016.1 and I try to use VIO and ILA in a same design. At the beginning, I can read back data and display waveform from the ILA core. After I adding 4 new probes of signals into the ILA, then I can trigger it but it corrupted when it uploading data and no waveform been displayed. I can get the error message shown in the image below.
The clock connected to the ILA is a 200Mhz free running clock from a crystal, and the JTAG clock is a 6Mhz clock. I also tried a 3Mhz JTAG clock and it didn't work either. After that, I will try to reduce the number of signals connected to the ILA later. I wonder know the number limits that I can connect to the ILA core by the setup debug tool in VIVADO.
Thanks.
07-21-2017 01:41 AM
Hi @dreamertom,
Is timing met for the design?
07-21-2017 01:49 AM
I find that I forget adding the clock timing constraints. I will try again after adding it.
07-23-2017 11:05 AM
Hi @dreamertom,
Please ensure all timing constraints are met before debugging and you have properly constrained all the paths.
Please check the below Answer record:
https://www.xilinx.com/support/answers/62421.html
Regards,
Sravanthi B
07-23-2017 09:15 PM
Hi @dreamertom,
Are you able to debug after taking care of timing constraints?