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Adventurer
Adventurer
5,997 Views
Registered: ‎06-17-2015

Waveform window empty for new ILA

Hello everyone,

 

I have a design with 3 ILA. All of them work fine.

I added a fourth one, and it does not work. The waveform window is empty. I can see and add signals in the Trigger Setup, though.

 

The log is very helpful, stating that an "unknown error occurred"...

 

I tried so far

-assigning signals to probes in clock and non clocked environment

-creating a new ILA instead of reinstantiating on of the three working ones

-rebooting the machine and regenerating the bitstream

-cleaning up project files and regenerating the bitstream

 

What can be the reasons for this behaviour?

 

Best regards,

 

Johannes

 

#-----------------------------------------------------------
# Vivado v2016.1 (64-bit)
# SW Build 1538259 on Fri Apr  8 15:45:27 MDT 2016
# IP Build 1537824 on Fri Apr  8 04:28:57 MDT 2016
# Start of session at: Wed Aug 03 11:21:48 2016
# Process ID: 11244
# Current directory: C:/Users/muellers/AppData/Roaming/Xilinx/Vivado
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent11708
# Log file: C:/Users/muellers/AppData/Roaming/Xilinx/Vivado/vivado.log
# Journal file: C:/Users/muellers/AppData/Roaming/Xilinx/Vivado\vivado.jou
#-----------------------------------------------------------
start_gui
open_project D:/Workspaces/muellers/Vivado/SADC64_GIT/project/sadc64.xpr
CRITICAL WARNING: [Project 1-19] Could not find the file 'D:/Workspaces/muellers/Vivado/SADC64_GIT/ip_repo/CLK_MNGR/CLK_MNGR.upgrade_log'.
CRITICAL WARNING: [Project 1-19] Could not find the file 'D:/Workspaces/muellers/Vivado/SADC64_GIT/ip_repo/ila_eth/ila_eth.upgrade_log'.
CRITICAL WARNING: [Project 1-19] Could not find the file 'D:/Workspaces/muellers/Vivado/SADC64_GIT/ip_repo/ila_fe/ila_fe.upgrade_log'.
CRITICAL WARNING: [Project 1-19] Could not find the file 'D:/Workspaces/muellers/Vivado/SADC64_GIT/ip_repo/mac_encoder_fifo/mac_encoder_fifo.upgrade_log'.
CRITICAL WARNING: [Project 1-19] Could not find the file 'D:/Workspaces/muellers/Vivado/SADC64_GIT/ip_repo/ila_mdio/ila_mdio.upgrade_log'.
CRITICAL WARNING: [Project 1-19] Could not find the file 'D:/Workspaces/muellers/Vivado/SADC64_GIT/ip_repo/tri_mode_ethernet_mac_0/tri_mode_ethernet_mac_0.upgrade_log'.
CRITICAL WARNING: [Project 1-19] Could not find the file 'D:/Workspaces/muellers/Vivado/SADC64_GIT/ip_repo/vio_transceiver/vio_transceiver.upgrade_log'.
CRITICAL WARNING: [Project 1-19] Could not find the file 'D:/Workspaces/muellers/Vivado/SADC64_GIT/ip_repo/vio_fe/vio_fe.upgrade_log'.
CRITICAL WARNING: [Project 1-19] Could not find the file 'D:/Workspaces/muellers/Vivado/SADC64_GIT/ip_repo/vio_eth/vio_eth.upgrade_log'.
CRITICAL WARNING: [Project 1-19] Could not find the file 'D:/Workspaces/muellers/Vivado/SADC64_GIT/ip_repo/vio_adc_slow/vio_adc_slow.upgrade_log'.
CRITICAL WARNING: [Project 1-19] Could not find the file 'D:/Workspaces/muellers/Vivado/SADC64_GIT/ip_repo/vio_adc/vio_adc.upgrade_log'.
CRITICAL WARNING: [Project 1-19] Could not find the file 'D:/Workspaces/muellers/Vivado/SADC64_GIT/ip_repo/fifo_56x16/fifo_56x16.upgrade_log'.
CRITICAL WARNING: [Project 1-19] Could not find the file 'D:/Workspaces/muellers/Vivado/SADC64_GIT/ip_repo/ila_udp/ila_udp.upgrade_log'.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2016.1/data/ip'.
WARNING: [IP_Flow 19-2162] IP 'gig_ethernet_pcs_pma_0' is locked:
* IP 'gig_ethernet_pcs_pma_0' is configured as a user-managed IP. In this mode it is the user's responsibility to manage all IP files.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
open_project: Time (s): cpu = 00:00:29 ; elapsed = 00:00:23 . Memory (MB): peak = 1212.773 ; gain = 531.691
update_compile_order -fileset sources_1
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2016.1
  **** Build date : Apr  8 2016-16:12:32
    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.


open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/00000000000000
set_property PROGRAM.FILE {D:/Workspaces/muellers/Vivado/SADC64_GIT/project/sadc64.runs/impl_1/TOP.bit} [lindex [get_hw_devices] 0]
set_property PROBES.FILE {D:/Workspaces/muellers/Vivado/SADC64_GIT/project/sadc64.runs/impl_1/debug_nets.ltx} [lindex [get_hw_devices] 0]
current_hw_device [lindex [get_hw_devices] 0]
refresh_hw_device [lindex [get_hw_devices] 0]
INFO: [Labtools 27-2302] Device xc7k160t (JTAG device index = 0) is programmed with a design that has 4 ILA core(s).
INFO: [Labtools 27-2302] Device xc7k160t (JTAG device index = 0) is programmed with a design that has 3 VIO core(s).
WARNING: [Labtools 27-1952] VIO hw_probe OUTPUT_VALUE properties for hw_vio(s) [hw_vio_2] differ from output values in the VIO core(s).
Resolution: 
To synchronize the hw_probes properties and the VIO core outputs choose one of the following alternatives:
  1) Execute the command 'Commit Output Values to VIO Core', to write down the hw_probe values to the core.
  2) Execute the command 'Refresh Input and Output Values from VIO Core', to update the hw_probe properties with the core values.
  3) First restore initial values in the core with the command 'Reset VIO Core Outputs', and then execute the command 'Refresh Input and Output Values from VIO Core'.
refresh_hw_device: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1258.988 ; gain = 9.742
display_hw_ila_data [ get_hw_ila_data hw_ila_data_1 -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7k160t_0] -filter {CELL_NAME=~"ethernet_inst/ila_eth_inst"}]]
display_hw_ila_data [ get_hw_ila_data hw_ila_data_2 -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7k160t_0] -filter {CELL_NAME=~"feature_extract_inst/ila_fe_inst"}]]
display_hw_ila_data [ get_hw_ila_data hw_ila_data_3 -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7k160t_0] -filter {CELL_NAME=~"ila_udp_inst"}]]
display_hw_ila_data [ get_hw_ila_data hw_ila_data_4 -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7k160t_0] -filter {CELL_NAME=~"ip_tx_arbiter_inst/ila_txarb_inst"}]]
ERROR: unknown error occurred

 

vivado_problem_empty_wf.PNG

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5 Replies
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Xilinx Employee
Xilinx Employee
5,985 Views
Registered: ‎08-01-2008

Re: Waveform window empty for new ILA

check this post
https://forums.xilinx.com/t5/Design-Tools-Others/ILA-AXI-waveform-window-empty/td-p/671905
Thanks and Regards
Balkrishan
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Adventurer
Adventurer
5,977 Views
Registered: ‎06-17-2015

Re: Waveform window empty for new ILA

No offense @balkris but the issue does not seem related to mine, and I have of course read all related threads that looked like a similar issue. As I have stated in my post I have tried to reboot the machine, which apparently solved the issue for @sibythachil.

 

Apart from that, a software should not behave differently after a reboot of the computer. I am working on a terminal server that I can not reboot at will - but I did, to exclude it as a source of the problem.

 

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Moderator
Moderator
5,970 Views
Registered: ‎07-01-2015

Re: Waveform window empty for new ILA

Hi @cbhiskp,

 

What are the clock frequencies and JTAG frequencies of your design? Is the scenario same with all ILA dashboards?

 

Thanks,
Arpan
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Adventurer
Adventurer
5,964 Views
Registered: ‎06-17-2015

Re: Waveform window empty for new ILA

JTAG is running at 6MHz.

The problematic ILA is running with a clock of 125MHz. Another ILA, that is also instantiated manually, work fine within the same clock domain.

Two more ILAs run fine at 80MHz.

 

Best regards,

Johannes

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Highlighted
Moderator
Moderator
5,949 Views
Registered: ‎01-16-2013

Re: Waveform window empty for new ILA

Hi,

To narrow down the issue.
Is it possible for you to create one more image with only non working ILA?
I suspect that ILA is still under IDLE state and trigger has not occurred. Check the trigger condition whether it ever meet or not. Also try to run using immediate trigger.

If immediate trigger works then definitely the issue is with trigger condition.

Suggestion 2:
If trigger condition is meeting and ILA is no more in IDLE but in buffer state then check what is the buffer size you have set for ILA buffer is nothing but the samples you are looking for. If the buffer is not completed for ex. if 1024 you have set and it is not able to capture 1024 samples due to conditions of signal toggle tool can't show results.

Suppose you only wants 200 sample but due to limitation can't set buffer to 200 partial buffer capture is also available try that.

I am asking to create new image as single ILA issue will give you more clear idea about the root cause.

Thanks,
Yash
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