UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
878 Views
Registered: ‎05-01-2018

Write data to memory from PC

Jump to solution

Hi

I have a design including a memory IP and some logic to use data from this memory block. Now, I want to sent data to this block from my computer using a JTAG interface or others. Can this be done with the LogicCore Debug Bridge? Or are there other solutions? Could you provide me with some documents?

Kind regards

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Advisor evgenis1
Advisor
1,088 Views
Registered: ‎12-03-2007

Re: Write data to memory from PC

Jump to solution

Hi @theinquisitor9 , 

 

I have good experience using Vivado JTAG to AXI Master IP Core [link] to read and write data to different modules inside FPGA design. It's fairly simple to write a TCL script and run it from Vivado GUI or TCL console to automate things.

 

Hope that helps,

Evgeni

View solution in original post

Tags (1)
2 Replies
Highlighted
Advisor evgenis1
Advisor
1,089 Views
Registered: ‎12-03-2007

Re: Write data to memory from PC

Jump to solution

Hi @theinquisitor9 , 

 

I have good experience using Vivado JTAG to AXI Master IP Core [link] to read and write data to different modules inside FPGA design. It's fairly simple to write a TCL script and run it from Vivado GUI or TCL console to automate things.

 

Hope that helps,

Evgeni

View solution in original post

Tags (1)
Moderator
Moderator
845 Views
Registered: ‎02-09-2017

Re: Write data to memory from PC

Jump to solution

Hi @theinquisitor9,

 

Adding to @evgenis1, I also believe the JTAG-to-AXI core is what you would want.

 

You can verify the document Vivado Design Suite Tutorial, Programming and Debugging - UG936, Lab 9: Using Vivado ILA Core to Debug JTAG-AXI Transactions.

 

This document has an explanation and example design for the JTAG-to-AXI core, as well as how to connect it to an ILA in case you want to also visualize the data. It also contains examples of how to issue the TCL read and write transactions to get information in and out of specific memory addresses.

 

Thanks.

Andre Guerrero

Product Applications Engineer

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos