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simon_tam_gmail
Contributor
Contributor
1,040 Views
Registered: ‎08-20-2019

XPE 2020.1 displays #N/A

Hi,

   I exported a XPE file from a Vivado 2019.2 project and imported it in XPE US+ 2020.1. I got the following results. I don't think this is a regional setting issue like the other posts. My XPE file is attached. 

Capture.PNG

   Please comment if you have suggestion. 

 

Thanks,

 

Simon

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6 Replies
gnarahar
Moderator
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977 Views
Registered: ‎07-23-2015

@simon_tam_gmail Thanks for reporting this out. I am looking into this and will get back. 

Please use 2019.2.1 XPE until then. Let me know if you don't have this version and I will send it across. 

- Giri
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gnarahar
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Registered: ‎07-23-2015

@simon_tam_gmail This happening due to the VCU block power. 

Though not a clean workaround, steps to get going

  1. Note down the VCU Dynamic Power for the rails in VCU section ("Other" sheet)
  2. Power Down the VCU (cell E12)
  3. Use XPE to make further adjustments
  4. Add the "noted" dynamic power with an additional 0.2W static (worst case) to Total Power 

I have filed a CR on this and it will be fixed in the next revision. 

 

- Giri
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Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
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simon_tam_gmail
Contributor
Contributor
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Registered: ‎08-20-2019

Hi Giri,

   Yes please send 2019.2.1 XPE to me. I couldn't find it on Xilinx site.

thanks,

Simon

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gnarahar
Moderator
Moderator
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Registered: ‎07-23-2015

@simon_tam_gmail Done. Sent to your email

- Giri
------------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
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dbellix
Newbie
Newbie
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Registered: ‎07-22-2020

Hello,

@gnaraharplease, can you share the XPE also with me? davide.bellizia@uclouvain.be

Thanks in advance

Best,

DB

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gnarahar
Moderator
Moderator
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Registered: ‎07-23-2015

@dbellix Done. sorry was off and so the delay

- Giri
------------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
------------------------------------------------------------------------------------------------------------------------

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