05-08-2014 05:40 AM
Hi I'm currently analysing xpower results of different components, and struggling with Error 1653:
ERROR:Power:1653 - Duty cycle <200.00> must be in range [0..100]%
In order to investigate what causes this Error, i found some forum threads, that have different solution, but won't help to understande how this duty cycle is calculated and why it may become larger than the designated range.
I have different values for the error (this is just part of the hole error log):
ERROR:Power:1653 - Duty cycle <200.00> must be in range [0..100]% for xin2<1>. ERROR:Power:1653 - Duty cycle <136.00> must be in range [0..100]% for delay_bph_d0<7>. ERROR:Power:1653 - Duty cycle <179.00> must be in range [0..100]% for delay_dltx_address1<2>. ERROR:Power:1653 - Duty cycle <186.00> must be in range [0..100]% for delay_dltx_address1<0>. ERROR:Power:1653 - Duty cycle <105.00> must be in range [0..100]% for delay_bpl_d0<7>.
Now i determined other information i can get within the power report e.g. the toggling rate and the % High (second nummer 100, 91, 92...)
name Rate % High Duty Cycle from error 3.3.2IO xin2<1> 1.39 100 200 126.96.36.199. Signals delay_bph_d0<7> 5.56 91 136 188.8.131.52. Signals delay_dltx_address1<2> 8.33 92 179 184.108.40.206. Signals delay_dltx_address1<0> 2.78 97 186 220.127.116.11. Signals delay_bpl_d0<7> 2.78 99 105
So do these values have any connection to each other, or can I ignore the error? It would be very nice to have an idea of what the error really means and how this duty cycle is calculated.
05-08-2014 05:51 AM
check this thread: http://forums.xilinx.com/t5/Design-Tools-Others/Error-on-Xpower/td-p/313501
05-08-2014 06:41 AM
I was aware of this post, but it doesn't help,
"For the LSB of a counter, on 100 MHz clock, that is 1/2 100 (50% duty cycle), or 50 MHz....etc."
That is true and understandable, the duty cycle in this example is 50. But for a toggle rate of 1.39 which formula do i have to use to get to a duty cycle of 200. I thought duty is somehow equivalent to % of time high.
Also according to the post, large parts of my designs have to be implemented in DDR with strange rates (strange values for 2)