XVC error: Waveform data read from ILA core is corrupted
we are facing a problem when using the XVC debug tool.
Our HW/SW infrastructure is:
Processor board: ABACO SBC326 3U VPX Single Board Computer with Yocto OS. The XVC driver and server are running on this board and are compiled for Vivado 2019.1 release. This board is connected via PCIe to the FPGA board.
FPGA board: custom board that hosts an Artix-7. We used Vivado 2019.1 release and the HW design inside the FPGA (at least part of it) is the following:
The 2 key modules are: PCIe endopoint DMA/Bridge Subsystem for PCIe Express 4.1 (x4 5.0 GT/s) connected to the Debug Bridge IP configured in AXI mode.
As an example we want to monitor a 16 bit counter with the ILA named ila_cnt.
As debug tool we use Vivado 2019.1 on a separate PC connected to the Processor board via Ethernet. We are able to establish an XVC connection with the boards chain (as a proof we see the ILA as expected when we upload the .ltx associated file).
The problems arise when we trigger the ILA. In particular we have these two kinds of problems.
This is when we set the option "Trigger position in window" to a value different from 0 (see the red message on the tcl console).
This is when we set the option "Trigger position in window" to a value equal to 0 (see the waveform window). We don't see the previous red message but, as you can see, starting from sample 78 Vivado doesn't show any real information (the samples are constantly zero but the counter is running).
In this case the XVC server is showing this error:
We also tested this on different version of Vivado (eg. 2017.4) and different FPGA board that hosts different FPGA (Ultrascale ku115) but we faced the same kind of problems. When we use JTAG debug instead the XVC tool we can see what we expect (eg. no zero samples shown on the ila_cnt).
In which direction we can move to solve this problem? It seams to be an error when the XVC server try to retrive data from debug core.