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Visitor mathaide
Visitor
8,016 Views
Registered: ‎12-07-2015

Xilinx Coolrunner II XC2C256 CPLD Verilog programming issue

My company is currently having a problem with our Xilinx CPLD programming. The main issue comes from (I believe) the fact that we are using our strobe signal as a clock. We are supposed to be getting 2 strobes and the second strobe depends on the first strobe, however, it appears as if we are getting extra strobes and the software is getting out of sync with the strobes. There are no clocks on a CPLD, so how do I fix this so that I don't have the race condition I seem to be getting?

 

module Module1
   (
      // Causal signals
   input            I_strobe_n,
   input            I_mode,
   input      [7:0] I_addr,
   output reg [8:0] O_pindrive1 = 9'h1FF,
   output reg [8:0] O_pindrive2 = 9'h1FF,
   output reg Selector1 = 1,
   output reg Selector2 = 1
   );
   reg   [8:0] cntr_value = 9'h000;
   reg   ghost_filt = 0;
   reg   [8:0] lut_value0 = 9'h000;
   reg   [8:0] lut_value1 = 9'h000;
   reg   [8:0] lut_value2 = 9'h000;
   reg   First = 1;
   always @ (posedge I_strobe_n)
        if(First == 1)                                                           //First Strobe
        begin
            First = 1'b0;
            begin
                     Selector1 = I_addr[1];                                //I did go through and change all the "=" to "<=" and that didn't seem to
                     Selector2 = ~I_addr[1];                              //have any difference either.
                     ghost_filt = 1'h0;
                     begin
                              if(I_addr[1])
                                     O_pindrive1 <= 9'h1FF;
                              else
                                     begin
                                           if(~I_addr[0])
                                                     ghost_filt = 1'h1;
                                           O_pindrive2 <= 9'h1FF;
                                     end
                             if(I_addr[7])
                                     cntr_value = 9'h1FF;
                     end
              end
        end
        else                                                                           //Second Strobe
            begin
                First = 1'b1;
                if (I_mode) //Case statement mode
                    begin
                        if(~Selector1 & ghost_filt)
                             O_pindrive1 <= lut_value0;
                     else if(~Selector2)
                             O_pindrive2 <= lut_value2;
                        else
                            O_pindrive1 <= lut_value1;
                    end
                else //Count mode
                begin
                    cntr_value = cntr_value + 1'b1;
                    begin
                        if(~Selector1)
                            O_pindrive1 <= cntr_value;
                        else
                            O_pindrive2 <= cntr_value;
                    end
                end
            end


    always @ (I_addr)
        case (I_addr)
         8'h00:
                begin
         lut_value1 <= 9'h007;
         lut_value2 <= 9'h007;
         lut_value0 <= 9'h00E;
                end
         8'h01:
                begin
         lut_value1 <= 9'h007;
         lut_value2 <= 9'h007;
         lut_value0 <= 9'h00E;
                end
         8'h02:
                begin
         lut_value1 <= 9'h007;
         lut_value2 <= 9'h007;
         lut_value0 <= 9'h00E;
                end
         8'h03:
                begin
         lut_value1 <= 9'h007;
         lut_value2 <= 9'h007;
         lut_value0 <= 9'h00E;
                end

 

//and so on for the case statement....

 

        endcase
endmodule

 

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3 Replies
Professor
Professor
7,960 Views
Registered: ‎08-14-2007

Re: Xilinx Coolrunner II XC2C256 CPLD Verilog programming issue

Are you saying that each command consists of two strobes, and the only way you can tell the first from the second is by keeping track using your "First" toggle signal?  I fail to see how you can solve this issue without having more information from the interface.  Suppose your CPLD code was rock solid and never missed a pulse.  Still if you just happened to start up between first and second pulses of a command, you would be out of sync forever.  If the only way to tell a "first" pulse from a "second" pulse is in the timing, e.g. the two pulses always come within "X" nanoseconds of eachother, but inter-command gaps can be much larger, then you could get into sync using the timing of the interface.  However you would need a free-running clock for that.

-- Gabor
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Visitor mathaide
Visitor
7,925 Views
Registered: ‎12-07-2015

Re: Xilinx Coolrunner II XC2C256 CPLD Verilog programming issue

The problem is that I don't have a clock and I have no idea how to do this without a clock. Is there a way to cause delays and such without a clock? 'Timespec' is not recognized by this CPLD and neither are just about all the other timing syntax that can be used by FPGAs. 

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Professor
Professor
7,913 Views
Registered: ‎08-14-2007

Re: Xilinx Coolrunner II XC2C256 CPLD Verilog programming issue

Just to be clear, timespec and associated # delays in Verilog are ignored for synthesis, even when they are legal.  To get a real delay in hardware, you need some sort of delay element in the fabric.  For a CPLD, you could make a ring oscillator using macrocells, but that would typically run very fast, and need significant resources to divide down to a frequency usable for timing.  It would also be highly process dependent, so you could only use it for relative timing due to the lack of accuracy.  You could also look at using a couple of spare IO pins to create an RC oscillator if your device has the option for hysteresis on inputs.

-- Gabor
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