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kam1314
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Registered: ‎08-29-2018

Zynq 7000 Linux zc706

Good afternoon, I ran into this problem:
compiled an SD card image which includes BOOT BIN (FSBL, Bit file, U-BOOT (xilinx 2019.1 branch)), uImage, devicetree.
after booting I turn on in Vivado Hardware Manager and try
connect to Debug Core:
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN ​​[get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-3413] Dropping logic core with cellname: 'u_ila_0' at location 'uuid_23E7D65A79BC59F7BC47406C1714DFAE' from probes file, since it cannot be found on the programmed device
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the clock input of the Debug Hub and iLA is connected FCLKCLK0 which is connected to the Zynq PS. As I understand it, the problem occurs due to incorrect initialization of the Zynq PS, apparently the clock is not active so the Hardware Manager does not see it.
what changes need to be made to FSBL or uBoot in order to start the clock clock correctly FCLKCLK0

i am using VIVADO 2019.1 SDK 2019.1

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