cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
mglorieux
Visitor
Visitor
3,386 Views
Registered: ‎06-28-2017

Zynq U+ ILA vector range check

Jump to solution

Hi,

 

I try to implement a Vivado Integrated Logic Analyzer (ILA) in the FPGA section of a ZU3EG-ES1 device.

I generated the core using the GUI, instantiated it, and ran the synthesis and implementation flow without issue (as I have already done on Kintex7).

 

My issue is related to the usage of the ILA in the hardware manager. I power-up the device, I configure the FPGA and release the reset of the processor (clock is derived from the processing system) from the SDK. Clock propagates correctly to the FPGA as my PLLs locks (observed on LEDs). However, when I refresh the device in vivado hardware manager, using the correct debug probe files, I have the following message in the console :

refresh_hw_device [lindex [get_hw_devices xczu3_0] 0]
INFO: [Labtools 27-2302] Device xczu3 (JTAG device index = 0) is programmed with a design that has 1 ILA core(s).
vector::_M_range_check: __n (which is 5) >= this->size() (which is 5)

 

The core is then not usable as vivado cannot map the signals.

Is my procedure to configure the device is correct? What is the meaning of this message and how to solve this issue?

 

Regards

 

 

0 Kudos
Reply
1 Solution

Accepted Solutions
mglorieux
Visitor
Visitor
5,582 Views
Registered: ‎06-28-2017

Hi,

 

I found the solution: The ILA clock frequency in the hierarchy of my design was to slow (it must be twice the JTAG frequency, as pointed out here : https://forums.xilinx.com/t5/Design-Tools-Others/need-a-slow-clock-for-ILA/m-p/775890#M10561)

 

Thanks for your help!

 

View solution in original post

0 Kudos
Reply
5 Replies
arpansur
Moderator
Moderator
3,379 Views
Registered: ‎07-01-2015

Hi @mglorieux,

 

Which version of the tool you are using?

 

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Reply
mglorieux
Visitor
Visitor
3,370 Views
Registered: ‎06-28-2017

Hi Arpansur,

 

Thanks for your reply.

I am using 2017.1

 

Regards,

0 Kudos
Reply
arpansur
Moderator
Moderator
3,362 Views
Registered: ‎07-01-2015

Hi @mglorieux,

 

Can you try with System ILA?

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Reply
mglorieux
Visitor
Visitor
3,322 Views
Registered: ‎06-28-2017

Hi Arpan,

 

Thanks for your suggestion.

I made several trials:

- Implementing the system ILA in the same block design as the ZYNQ processor (hierarchical level 1) => works

- Implementing the system ILA in a different block design, and instantiate it in my FPGA design hierarchy (level 2), as I did with the ILA => does not work: Same message about vector range

- Try with 2017.2 tools, with the ILA (not system ILA) => does not work, with the same error message.

 

Thanks for your support

0 Kudos
Reply
mglorieux
Visitor
Visitor
5,583 Views
Registered: ‎06-28-2017

Hi,

 

I found the solution: The ILA clock frequency in the hierarchy of my design was to slow (it must be twice the JTAG frequency, as pointed out here : https://forums.xilinx.com/t5/Design-Tools-Others/need-a-slow-clock-for-ILA/m-p/775890#M10561)

 

Thanks for your help!

 

View solution in original post

0 Kudos
Reply